International Business Machines Corporation

Globalfoundries Inc.

Jack Oon Chu

Alfred Grill

Jeng-Bang Yau

John Albrecht Ott

Khalid EzzEldin Ismail

Kevin K Chan

Steven John Koester

Qiqing Christine Ouyang

Katherine Lynn Saenger

Christos Dimitrios Dimitrakopoulos

Basanth Jagannathan

Isaac Lauer

Devendra K Sadana

Cyril Cabral, Jr

Paul Michael Solomon

Robert L Wisnieff

Leathen Shi

Ryan Wayne Wuthrich

Szu-Lin Cheng

Meikei Ieong

Timothy James McArdle

Kam-Leung Lee

Patricia May Mooney

Stephen W Bedell

Guy M Cohen

Cheng-Wei Cheng

Ahmet Serkan Ozcan

Bernard S Meyerson

Yanning Sun

John Bruley

Louis L Hsu

Kuen-Ting Shiu

David Louis Harame

James Stuart Dunn

Kathryn Turner Schonenberg

James M Harper

Louis DeWolf Lanzerotti

David R Greenberg

Young-Hee Kim

Bruce Bennett Doris

Christian Lavoie

Kern Rim

Douglas Duane Coolbaugh

Dirk Pfeiffer

Harold John Hovel

Kathryn Wilder Guarini

Roy Arthur Carruthers

Jeremy Daniel Schaub

Huiling Shang

Marcus Oliver Freitag

Jing Wang

Jack Allan Mandelman

Keith E Fogel

Ying Di Zhang

Jeehwan Kim

Kerry Bernstein

Martin Michael Frank

Kim Yang Lee

Deborah A Neumayer

Solomon Assefa

Donald Francis Canaperi

William M Green

Chun-Yung Sung

Christy Sensenich Tyberg

Ronnen Andrew Roy

Can Bayram

Michael Joseph Rooks

George Gabriel Totir

Joris Van Campenhout

Hongsik Park

Paul Andrew Ronsheim

Ageeth Anke Bol

David C Ahlgren

Yuan Taur

Alexander Reznicek

Jeffrey P Gambino

Vijay Narayanan

Dureseti Chidambarrao

Judson Robert Holt

Kenneth Parker Rodbell

Stephen McConnell Gates

Conal Eugene Murray

Yurii A Vlasov

David Edward Kotecki

Hon-Sum Philip Wong

Michael F Lofaro

John Rozen

Joseph F Shepard

Anthony Gene Domenicucci

Seshadri Subbanna

Gregory M Fritz

Chang-Ming Hsieh

Christopher Peter D'Emic

Byeongju Park

Francois Pagette

Anda C Mocuta

Eric C Harley

Manu J Tejwani

Scott R Stiffler

Matthew W Stoker

A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.

Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements

An electronic device includes a spreading layer and a first contact layer formed over and contacting the spreading layer. The first contact layer is formed from a thermally conductive crystalline material having a thermal conductivity greater than or equal to that of an active layer material. An active layer includes one or more III-nitride layers. A second contact layer is formed over the active layer, wherein the active layer is disposed vertically between the first and second contact layers to form a vertical thin film stack.

Thin film wafer transfer and structure for electronic devices

A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins.

III-V MOSFET with self-aligned diffusion barrier

A scaled dielectric stack interlayer, compatible with subsequent high temperature processing with good electrical transport & reliability properties is provided. A method for forming a conformal aSi:H passivation layer on a semiconductor device is described. A patterned semiconductor wafer is placed in in a process chamber with a first layer formed thereon and a second layer formed thereon, the first layer and the second layer being two different materials Next, a SiHbased deposition up to a temperature of 400 degrees Celsius is used on the first layer and the second layer thereby forming a conformal aSi:H passivating layer is formed at a higher rate of deposition on the first layer selectively and a lower rate of deposit on the second layer.

Selective and conformal passivation layer for 3D high-mobility channel devices

A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source including III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer including silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer including transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer including transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.

A semiconductor structure includes a plurality of semiconductor fins located on a semiconductor substrate, in which each of the semiconductor fins comprises a sequential stack of a buffered layer including a III-V semiconductor material and a channel layer including a III-V semiconductor material. The semiconductor structure further includes a gap filler material surrounding the semiconductor fins and including a plurality of trenches therein. The released portions of the channel layers of the semiconductor fins located in the trenches constitute nanowire channels of the semiconductor structure, and opposing end portions of the channel layers of the semiconductor fins located outside of the trenches constitute a source region and a drain region of the semiconductor structure, respectively. In addition, the semiconductor structure further includes a plurality of gates structures located within the trenches that surround the nanowire channels in a gate all around configuration.

Nanowire field effect transistor (FET) and method for fabricating the same

A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.

Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

Carbon nanostructure device fabrication utilizing protect layers

A method for manufacturing a semiconductor device, comprises forming an organic planarization layer on a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, forming an oxide layer on the organic planarization layer, removing a portion of the oxide layer to expose the organic planarization layer, stripping the organic planarization layer to form a cavity, patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity, and depositing a conductive contact in a remaining portion of the cavity.

Method of manufacturing a semiconductor device using a self-aligned OPL replacement contact and patterned HSQ and a semiconductor device formed by same

A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.

Method of manufacturing a semiconductor device using source/drain epitaxial overgrowth for forming self-aligned contacts without spacer loss and a semiconductor device formed by same

Growing community of inventors

Manhasset Hills, NY, United States of America

Jack Oon Chu