Vanguard International Semiconductor Corporation

Jack-Lian Kuo

Howard Clayton Kirsch

Yen-Tai Lin

Chiun-chi Shen

Jiang-Hong Ho

An apparatus having an input node and an output node for generating a timing signal. The apparatus includes an enabling circuit, one or more inverters, and one or more capacitive elements. The enabling circuit generates a signal of a first state when one or both of the input node and the output node are of a second state, and generates a signal of the second state when both of the input node and the output node are of the first state. The first state and the second state represent two opposite logic states. The inverters generate opposite state outputs in responsive with their inputs. The inverters are connected in series with a first inverter being responsive to the enabling circuit and a last inverter for generating a signal for the output node. The capacitive elements are connected between a voltage source and one of the inputs of the inverters.

Apparatus for generating a timing signal

This invention describes a delay circuit for integrated circuits that has the capability to delay the rising and falling transitions separately and independent of each other. A signal is fed through an RC network to a Schmitt trigger and then through an inverter to the output of the delay circuit. Two MOS transistors are connected as capacitors and in parallel but in opposing directions between the delay circuit output and the input to the Schmitt trigger to form part of the RC network. The biasing of the two transistors is such that the inversion layer capacitance is active in only one transistor for each signal transition. Thus the falling and rising transition of an input signal can be delayed separately. Changing the gate and channel size in one transistor acting as a capacitor changes the delay in one signal transition. Changing the other gate and channel size changes the delay in the other transition. The output of the delay circuit is fed back through the transistor capacitors to hasten the switching of the Schmitt trigger.

RC delay circuit for integrated circuits

Circuits and a method are described that integrate memory arrays, a redundant memory array, their associated decoders, sense amplifiers, and outputs into one module. This integration is achieved through the use of a column decoder with a fuse, which, when blown, permanently deselects the failing array and selects the redundant array. By OR'ing the redundant column select line of each column decoder, any column decoder can select the redundant array. Higher level array structures are produced by replication of the lower level array structure. The system output is generated by OR'ing together the respective data outputs of each array.

Semiconductor memory with a novel column decoder for selecting a

A circuit for the control of a power or ground distribution transient voltage or power bounce or ground bounce is described. The circuit has a driver transistor of a first conductivity type and a driver transistor of a second conductivity type connected so as to be able to transfer a voltage to a data output terminal from a I/O voltage distribution network or a I/O ground distribution network. As the output terminal changes from a logic 1 to a logic 0 the driver transistor of the first conductivity type will conduct and a ground distribution voltage transient will begin to appear. A suppression transistor of the first conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the first conductivity type decreasing the slew rate of the driver transistor of the first conductivity type. As the output terminal changes from a logic 0 to a logic 1 the driver transistor of the second conductivity type will conduct and a power distribution voltage transient will begin to appear. A suppression transistor of the second conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the second conductivity type decreasing the slew rate of the driver transistor of the second conductivity type. The transistors may be PMOS, NMOS, NPN bipolar, or PNP bipolar integrated upon a silicon or compound semiconductor substrate.

Growing community of inventors

Tainan, Taiwan

Jack-Lian Kuo