Creative Integrated Systems, Inc.

Rocoh Company, Ltd.

Creative Integrated Ststems, Inc.

Jack L Minney

James A Komarek

Clarence W Padgett

Scott B Tanner

John F Stockman

Harold F Lewis

Richard Wada

Stephen P Nordine

Keiji Fukumura

Motohiro Oishi

Shin-ichi Kojima

H Nakanishi

A circuit attenuates echo caused by line variations and a transformerless, high DC impedance, two-wire line interface. To reduce echo, a test tone is introduced on the communication line with all station units connected to the line. The resultant receive signal is conditioned through a peak detector, digitized and read by a processor. The resistive and capacitive characteristics of a network are iterated by the processor and the results remeasured. The network is set to the best combination for least echo by the processor. An interfacing system capacitively couples a plurality of sources to a two-wire communication pair by means of a plurality of differential voltage-to-current amplifiers. Each source uses a differential receiving amplifier to receive signals from the line and is resistively coupled in parallel to all the sourcing entities coupled to the communication line at that particular interface. There is an echo balance network associated with each source.

Circuit for attenuation of echos caused by line variations and an interfacing system for capacitively coupling a plurality of sources to a two-wire communication line

A small and economically fabricated CMOS voltage controlled crystal oscillator is provided by coupling three inverter amplifiers in series with a regenerative crystal controlled feedback loop. The first and second CMOS inverters have output nodes whose impedances are modified by a CMOS impedance modulating circuit. Also coupled to each of these two output nodes is a CMOS transistor shunt capacitor. The impedance of the output node is modified according to the magnitude of a voltage control signal applied to the CMOS modulating circuits. The self-bias of the modulating circuits is maintained substantially constant by adjusting the gate drive in each of the modulating circuits according to gate drives derived from a dummy modulating circuit. The dummy modulating circuit has as one input the voltage control signal and as its compensating gate drive, a control signal derived from a feedback loop from a dummy output node in such a manner that the self-bias of the dummy modulating circuit is maintained substantially constant. The compensating gate drive from the dummy modulating circuit is then coupled to the appropriate compensating gates within the impedance modulating circuits in the voltage controlled oscillator.

Home and small business phone system for operation on a single internal

An input receiver circuit in a read-only memory is provided with a feedback to control hysteresis. A second stage and an additional output is added to the receiver. Switching circuit noise from inside of the read-only memory is isolated by the added state and outputs, and cannot be fed back into the receiver circuit to affect the detection of the TTL voltage levels. Use of wide and long FET sizes minimizes the manufacture related variations in the input receiver switching levels.

NMOS input receiver circuit

A low power, low noise driving circuit for a bank of LEDs utilized in the station units of the MAN system is provided by coupling each bank of LEDs in a series circuit between the voltage supply and a constant current source. Each LED has a controllable logic switch in parallel across it and the switches are further in series circuit with each other to form a ladder network. Any selected LED may be turned off by closing its corresponding logic switch. The current continues to flow then through the shunting switch into the remaining LEDs in the series circuit that are on. A plurality of such ladder networks may be coupled in parallel with each other and each ladder network controlled by a switching gate which selectively couples it to the constant current source so that the LED ladder networks are operated at a predetermined duty cycle. Current spikes are avoided across the voltage supply by driving the connecting control gates in an overlapping relationship so that the constant current source is never disconnected from the voltage supply.

A memory precharge voltage, VPC, is provided which tracks changes in the high voltage supply, VDD, according to a measured degree, which maintains a precharge voltage notwithstanding transient loads which may tend to draw the precharge voltage down, and which maintains the precharge voltage at the operating level notwithstanding the fact that the precharge generator is substantially turned off during a power down condition. The precharge voltage, VPC, is then used as the controlling input signal to a circuit which it generates and an internal control voltage, MLC, used to drive small pull-up current FETs coupled to the bit lines in the ROM core. The internal control signal MLC is generated to track the discharge current in a bit line within the memory core, to track VPC, and to be maintained at its operating voltage level even when the MLC current is substantially turned off during a power down condition.

VLSI memory circuit

The invention is a telephone system capable of operating on a single internal telephone line as commonly found in the home or small businesses, which is economically implemented within an integrated circuit chip to provide a one chip telephone and which provides most of the components necessary for a full-featured, reliable and easy to install office communication system. The multiband audio network (MAN) transfers four audio bands and a digital data band over a single twisted pair of wire. A 6,000 bits per second full duplex digital data channel is also provided on the same twisted pair. Each station unit includes all the control and interface support necessary to perform conventional telephone functions. These functions include a combination of keyboard and display support circuitry such as strobe and debounce circuitry, LED buffers, piezo ring drivers, control registers and communication hardware. Everything needed to provide a programmably customized communication and telephone network is available using only one basic chip design in the system as described above. Not only are standard telephone communications possible on a single twisted pair, but a network of telephone receivers, computers, modems, telefax devices, answering machines and any other type of information handling or communication device now known or later devised for use on a telephone line can be networked and accommodated within the system.

The address transition detection circuit is improved by holding the previously latched address signal until a predetermined delay after receipt of the new address signal.

Semiconductor read-only VLSI memory

The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by a number of different improvements in various circuits and methodologies utilized in the memory. One of the improvements relates to control of an output buffer by a control circuit. The output enable signal to the output buffer is selectively inhibited by the control circuit which determines when the memory cycle is actually completed. Only after the memory cycle is actually completed is the conventional chip enable signal, CE, coupled to the enable input in the output buffer.

The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an output enable latch circuit which provides internal memory signal of whether the memory was operating in the standby or active mode during a previous memory cycle and a data latch circuit which provides an internal memory signal of whether a new read cycle is beginning within the memory. The data latch circuit is reset when address detection has occurred within the memory. A logic circuit combines an output of the data latch circuit, which is indicative of a memory read cycle, with an output of the output enable latch circuit, which is indicative of whether the prior memory cycle was standby or active. The logic circuit generates an output enable signal, OE, which is coupled to the output drivers of the memory to control float of the output drivers. As a result, a smooth transition from old data to new data is obtained, and system data bus contention in transitions from standby to active modes is eliminated.

Output driver control for ROM and RAM devices

Operation of an address latch circuit in a memory is conditioned on first receiving a ground surge control logic signal, SURG, which is generated only when data output drivers switch. This prevents noise from these same drivers from falsely addressing the memory. Metastability is prevented by selecting the trigger points of the gates which make up the latch such that an output is not generated until input or intermediate circuitry has stabilized and by providing a favored output condition in the input or intermediate circuitry when conflict between almost simultaneous inputs occur. Feedback of the output of the latch to its input further reduces metastability.

Very large scale integrated planar read only memory

The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.

A telephone communication system for communicating between a plurality of exterior telephone lines and a single common in-house two wire line is comprised of a control unit for coupling to the plurality of exterior telephone lines and for controlling communication between the plurality of telephone lines and the common two wire line. A plurality of station units are coupled remotely throughout the building to the common two wire line. The control unit communicates on the digital channel with the plurality of station units in a time frame subdivided into a plurality of time slots. A specified portion of each time slot is reserved for control communication between the control unit and each one of the plurality of station units. A synchronization signal is transmitted for phase locking all the station units to the control unit clock and a common frame synchronization signal is used to align all units in time. Each remote telephone or adapter box has a unique number assigned to it by the setting of a manual switch. Each number corresponds to a slot in a time frame. Thereafter all control signaling to a specific station unit occurs in a particular time slot.

The invention is a dynamic ROM design for read cycle interrupts. The clock scheme of the improved memory generates a primary start clock. The relatively long pulse time of START when high is provided for setting the latches. This pulse duration is controlled by PCOK or OWDN one shot circuit. When an address interrupt occurs early in the read cycle, while PCOK or OWDN clock is low, and START is high, these one shot circuits provide a simple means of restarting the cycle by continuing the precharge phase of the cycle with no effect on most of the secondary clocks in the memory. Only those clocks relating to the new address inputs are effected by the early interrupt. This results in less power dissipation and less bus noise.

Method for read cycle interrupts in a dynamic read-only memory

In a read-only memory core improved generation of a trigger signal, TRIG, is achieved through the use of a pair of cascaded CMOS differential amplifiers which are directly interconnected and directly coupled to a CMOS inverter from which the trigger signal, TRIG, is derived. The cascaded differential amplifiers have trigger points set by varying the channel widths of the input FETs to the CMOS differential amplifiers, or by adjusting the gains of the CMOS differential amplifiers to match the trigger point of the CMOS inverter coupled to its output. The trigger circuit is powered down to zero power dissipation whenever it is inactive.

The operation of the sense amplifier in a VLSI memory is improved by providing dummy bit lines corresponding to the ON state and OFF state of the memory cells, averaging the voltage on the dummy bit lines, and comparing that average to the bit line voltage to generate a differential sense output. Leakage currents and voltages common to both the dummy bit lines and selected bit line are thus cancelled out. Sense amplifiers incorporating this advantage may also be used in combination with a dynamic latch which is selectively disconnected from the memory array at all times other than during a memory cycle to avoid noise interference. Dummy word lines used in combination with dummy predecoder and decoder are used to make on-chip determinations of the transition points when an address signal is valid and complete. The actual initiation of the addressing of the memory may then be triggered according to a modeled transition point within each memory circuit. The worst ON state and OFF state voltages on dummy bit lines are used in a trigger circuit to generate a trigger signal for use in sense amplifiers which will reliably indicate when a valid sense decision can be made taking into consideration the individual process parameters and operating conditions of the actual memory circuit.

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Irvine, CA, United States of America

Jack L Minney