Delphi Technologies, Inc.

Delphi Technologies IP Limited

Jack L Glenn

Mark Wendell Gose

Seyed R Zarabadi

Kevin M Gertiser

John Mark Dikeman

Daniel C Penrod

Troy D Clear

Soumyajit Routh

John Carl Christenson

Dan W Chilcott

Kok Wee Yeo

Peter Allan Laubenstein

Pedro E Castillo-Borelly

Thomas W Kotowski

Alireza F Borzabadi

Gregg Nelson Francisco

Thomas E Pritchett

Richard G Forestal

Thomas K Simacek

Mark A Gose

Steven H Rogers

Doublas B Osborn

Nicholas T Campanile

Narendra J Mane

Gregg N Francisco

A method for assessing a thermal path associated with an integrated circuit includes identifying a heat application mode based on a design type of the integrated circuit. The method also includes measuring a first temperature of at least one thermal sensing device associated with the integrated circuit. The method also includes applying heat to at least a portion of the integrated circuit according to the heat application mode. The method also includes measuring a second temperature of the at least one thermal sensing device. The method also includes determining a difference between the first temperature and the second temperature. The method also includes determining whether a thermal path between the integrated circuit and an associated substrate is sufficient based on a comparison of the difference between the first temperature and the second temperature with a predetermined difference between an initial temperature and a subsequent temperature of the at least one thermal sensing device.

System and method for multi-point thermal path assessment

An electronic circuit includes a first pin corresponding to a reference signal and a second pin corresponding to an external resistor, the external resistor being connected on a first side to the second pin and connected on a second side to ground. The apparatus also includes a first oscillator having a first frequency loop configured to: receive, via the first pin, the reference signal; receive, via the second pin, a current associated with voltage applied to the external resistor; and lock a first frequency output at a frequency associated with the reference signal. The apparatus also includes a second oscillator having a second frequency loop configured to: receive the first frequency output; scale the frequency of the first frequency output; and lock a second frequency output at the scaled frequency of the first frequency output.

Dual oscillator partial-networking controller area network clock generator using a precision resistor reference

A method includes, responsive to an application of power to an IC, self-initializing the IC by asserting a reset signal for a reset period. Self-initializing the IC also includes, in response to an expiration of the reset period, deasserting the reset signal. Self-initializing the IC also includes, responsive to deasserting the reset signal, automatically obtaining first temperature data from at least one thermal sensing device associated with a die of the IC, and storing the first temperature data in a storage component of the IC.

Integrated circuit and method for capturing baseline die temperature data

A CAN transceiver includes a first terminal which receives a transmit signal from a CAN microcontroller. A splitter unit transmits a signal derived from the transmit signal to a CAN bus a via bus connection. A unit receives signals from the CAN bus via the bus connection. A second terminal sends a receive signal derived from the received signals to the CAN microcontroller. The transmit and receive signals include a pulsed signal waveform which represents data bits. Delay circuits apply a deliberate delay to the rising or falling edge of pulses of the transmit signal and/or a deliberate delay to the rising or falling edge of pulses of the receive signal.

Adaptable can transceiver and system

A rectifier circuit includes a MOSFET (M), and a first Zener diode (D) or a first Zener-emulator (E) that emulates the D. The circuit conducts current in a forward direction from an input to an output, and substantially blocks current in a reverse direction. The Mis characterized by an on-resistance. A cathode of the Dor a cathode-contact of the Eis connected to the input, and the anode of the Dor an anode-contact of the Eare connected to the source. The Eincludes a first small-Zener-diode (D), a first resistor (R) and a first transistor (M) interconnected such that the Eemulates the D, and is characterized by a Zener-voltage. The Zener-voltage and the on-resistance are selected such that a stored-charge in the body-diode is less than a forward-charge-threshold when current flows in the forward direction, whereby the reverse recover time of the body-diode is reduced.

Rectifier circuit with reduced reverse recovery time

A controller includes a high-side circuit, a low-side circuit, a level-shift circuit, and a data-validation circuit. The high-side circuit is referenced to an offset-voltage reference that is offset voltage-wise relative to a ground reference of the controller. The low-side circuit is operable to output a control signal for the high-side circuit. The control signal is referenced to the ground reference. The level-shift circuit is configured to output a shifted signal to the high-side circuit that is referenced to the offset-voltage reference and based on the control signal. The data-validation circuit is configured to receive the shifted signal, determine a first value of the shifted signal at a first instant, determine a second value of the shifted signal at a second instant different in time from the first instant, and validate the shifted signal based on a determination that the first value and the second value correspond.

Validation circuit for reference voltage shifted data

An apparatus and method of determining the junction temperature (Tj) and drain-source current (Ids) of a standard FET within a multi-FET module includes a control IC managing one or more 3 terminal standard FETs within the same package, calculating Tj and Tds for one or more FETs in one or more packages, and protecting each FET against short circuit faults while allowing high current transients, such as inrush currents from a lamp load.

Current and temperature sensing of standard field-effect transistors

A motion sensor in the form of an angular rate sensor and a method of making a sensor are provided and includes a support substrate and a silicon sensing ring supported by the substrate and having a flexive resonance. Drive electrodes apply electrostatic force on the ring to cause the ring to resonate. Sensing electrodes sense a change in capacitance indicative of vibration modes of resonance of the ring so as to sense motion. A plurality of silicon support rings connect the substrate to the ring. The support rings are located at an angle to substantially match a modulus of elasticity of the silicon, such as about 22.5 degrees and 67.5 degrees, with respect to the crystalline orientation of the silicon.

Method for manufacturing a sensor device

Electrostatic discharge (ESD) protection is provided for an integrated circuit. In an aspect, a dynamic region having doped regions is formed on an epitaxy layer and substrate, and interconnects contact the dynamic region. In an aspect, the dynamic region operates as a back-to-back SCR that snaps back in both positive and negative voltage directions. In an aspect the dynamic region operates as an SCR that snaps back in a positive voltage direction and operates as a simple diode in a negative voltage direction. In another aspect, the dynamic region operates as an SCR that snaps back in a negative voltage direction and operates as a simple diode in a positive voltage direction. ESD protection over an adjustable and wide positive and negative voltage range is provided by varying widths and positioning of various doping regions. Breakdown voltages, critical voltages and critical currents are independently controlled.

Method and device for electrostatic discharge protection

Electrostatic discharge (ESD) protection is provided for an integrated circuit. Snap back from a lower initial critical voltage and critical current is provided, as compared to contemporary designs. A dynamic region having doped regions is formed on a substrate, interconnects contacting the dynamic region. The dynamic region includes an Nwell region, a Pwell region and shallow diffusions, defining a PNP region, an NPN region and a voltage Breakdown region. In an aspect, the Nwell region includes a first N+ contact, a first P+ contact and an N+ doped enhancement, while the Pwell region includes a second N+ contact, a second P+ contact and a P+ doped enhancement. The N+ doped enhancement contacts the P+ doped enhancement forming the breakdown voltage region therebetween, in one case forming a buried breakdown voltage junction. Independent control is provided over breakdown voltage, NPN critical voltage, NPN critical current and PNP critical current, by varying doping levels, widths and positioning of various doping regions.

Method and apparatus for electrostatic discharge protection having a stable breakdown voltage and low snapback voltage

An integrated circuit (IC) with negative potential protection includes at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The IC also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket and a first-type+ ring formed through the first-type epitaxial pocket between the second-type+ isolation ring and the DMOS cell.

Technique for improving negative potential immunity of an integrated circuit

An electrostatic discharge (ESD) protection device includes a first-type substrate, a second-type well formed in the substrate and a first-type well formed in the substrate. The second-type well includes a second-type+ region formed between first and second first-type+ regions. The first-type well is formed in the substrate adjacent a first side of the second-type well. The first-type well includes first and second first-type regions with a first-type+ region and a second-type+ region formed between the first and second first-type regions. The second-type+ region of the first-type well is formed between the first-type+ region of the first-type well and the second-type well.

Electrostatic discharge protection device

A protection device for handling energy transients includes a plurality of basic unit Zener diodes connected in series to achieve a desired breakdown voltage. Each of the basic unit Zener diodes is formed in a first-type substrate. Each of the basic unit Zener diodes comprises a second-type well formed in the substrate, a second-type Zener region formed in the second-type well and a first-type+ region formed over the second-type Zener region between a first and second second-type+ region.

Protection device for handling energy transients

A programmable memory transistor (PMT) comprising an IGFET and a coupling capacitor in a semiconductor substrate. The IGFET comprises source and drain regions, a channel therebetween, a gate insulator overlying the channel, and a first floating gate over the gate insulator. The capacitor comprises a lightly-doped well of a first conductivity type, heavily-doped contact and injecting diffusions of opposite conductivity types in the lightly-doped well, a control gate insulator overlying a surface region of the lightly-doped well between the contact and injecting diffusions, a second floating gate on the control gate insulator, and a conductor contacting the lightly-doped well through the contact and injecting diffusions. The first and second floating gates are preferably patterned from a single polysilicon layer, such that the second floating gate is capacitively coupled to the lightly-doped well, and the latter defines a control gate for the first floating gate.

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Kokomo, IN, United States of America

Jack L Glenn