Bell Telephone Laboratories

Jack Kane

Richard A Pedersen

David Beecham

A low power high sensitivity detector having two pairs of MOS cross coupled transistors, voltage equalization circuitry, and a single input, with no external reference, forms the basic configuration of a detector-level shifter circuit which is compatible with today's single chip large capacity memories. The lengths of the channels of one of the pairs of cross coupled transistors are designed to be longer than the other pair. This provides a built-in imbalance which provides good tolerance to transistor parameter variation due to semiconductor processing variations.

Detector circuitry

A logic gate circuit includes a resistance divider input to the base of an input transistor and a multiple emitter output transistor in an emitter follower configuration. The circuit has favorable switching speed and power dissipation characteristics and reduces the effect of both capacitive loading and series resistance in signal interconnections. An efficient layout of one such logic circuit has intercell wiring channels formed across the circuit and has the inputs and outputs of the circuit arranged in two lines each of which crosses perpendicular to the wiring channels.

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Bethlehem, PA, United States of America

Jack Kane