Massachusetts Institute of Technology

Mass. Institute of Technology

Jack I Raffel

John A Yasaitis

Glenn H Chapman

Terry O Herndon

Simon S Cohen

Stephen E Bernacki

Mark L Naiman

Peter W Wyatt

F Matthew Rhodes

James A Burns

Methods and systems are discussed for fabricating electrically programmable link structures by fabricating a first metal conductor of a refractory conductive material, composite, or an aluminum alloy which has been modified with a refractory material, then fabricating an insulating link material over the first conductor, and subsequently, depositing a second conductor over the link material. In use, an electrical path can be formed between the first and second conductors by applying a voltage between such conductors across at least one selected region of the insulator, such that the insulating link material is transformed in the region and rendered conductive to form an electrical signal path.

Voltage programmable links for integrated circuits

An electrical path can be formed through a transformable insulator between first and second conductors by applying a voltage between such conductors across at least one selected region of the insulator. Much of the current required to complete the link is provided from parasitic capacitance of the writing circuit or from capacitance which is removable from the circuit during normal operations. As a result, small transistors of less than 100 microamps may be used in the writing circuit which applies the programming voltage.

Voltage programmable links programmed with low current transistors

An interconnection system for high performance electronic hybrids employs micro-machined features on a substrate to connect directly to miniature electronic components, such as integrated circuits. The micro-machined features may include posts for connecting to bonding pads of standard components and may also include rails for alignment of components and connections to specially made components.

Interconnection system for high performance electronic hybrids

A laser programmable integrated circuit chip has a plurality of logic modules organized as rows and columns. The modules and other chip components are connected by a grid-like array of conductors. The conductors are initially unattached. Customization occurs by fusing laser diffuseable links and severing cut points on the conductors. The modules have continuous conductor lines running through them. These conductor lines aid in testing and are useful in routing and error avoidance. The chip also contains test registers to test the array of logic modules, the input/output blocks, and the conductors.

Laser programmable integrated circuit

An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer and a second metal layer. Diffusion barrier may be employed between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

Method of forming conductive path by low power laser pulse

A method and apparatus for reliably forming low resistance links between two aluminum conductors deposited on an insulating polysilicon or amorphous silicon layer, employ a laser to bridge a lateral gap between the conductors. The apparatus and method are ideally suited for implementing defect avoidance using redundancy in large random access memories and in complex VLSI circuits. Only a single level of metal is employed and leads to both higher density and lower capacitance in comparison to prior techniques. Resistances in the range of one to ten ohms can be achieved for gap widths of approximately two to three microns.

Method and apparatus for forming low resistance lateral links in a

An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer, a second metal layer and diffusion barrier layers between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

Method of making a conductive path in multi-layer metal structures by

An improved metal dual insulator semiconductor capacitor memory is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. The invention also provides a method of reading stored information without disturbing adjacent cells. A small variable voltage is applied across a 'flat-band' portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell. Methods to fabricate the memory are also disclosed.

Capacitor memory and methods for reading, writing, and fabricating

A process is described which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means. This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide 'bump' at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.

Dielectric isolation method using shallow oxide and polycrystalline

A process is described which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means. This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n-epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide 'bump' at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.

Dielectric isolation using shallow oxide and polycrystalline silicon

An improved method for reading metal dual insulator semiconductor capacitor memories is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. According to the invention, a small variable voltage is applied across a selected cell or cells. The range of voltage includes a 'flat-band' portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. The unselected cells are maintained in a depletion state in which their capacitance is a minimum. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell.

Reading capacitor memories with a variable voltage ramp

Lead connections and packaging for integrated circuits are formed by processing elongated ribbon arrays of integrated circuit dice in groups prior to cutting the ribbon along its length to free the discrete integrated circuit products. The ribbon is adhered to the base of an elongated channel having at least one leg containing implanted lead-in conductors arranged therein as an axial series of axial arrays of conductors. The axial arrays are aligned with the circuits on the ribbons and interconnections therebetween are formed as photolithographically defined conductive coatings on a top surface of the ribbon extending from bonding pads of the integrated circuit to exposed conductor ends at a top end(s) of the leg(s). The channel ribbon assembly is cut into discrete circuits after forming such interconnections for all the circuits of the ribbon as a group. Each array of lead-in conductors is packed in high density and fans out from the channel to an array of low density lead-out conductors which may be plugged into sockets or otherwise macroscopically treated.

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Lexington, MA, United States of America

Jack I Raffel