International Business Machines Corporation

Jack Harvey Derenburger

Vernon John Legvold

Ronald David Martens

Steven Douglas Johnson

Edward George Butt

Michael T Benhase

Kevin J Ash

Brent Cameron Beardsley

Carl Evan Jones

Gary William Batchelor

Juan Antonio Yanes

Robert Earl Medlin

Raymond L Parsons

Allen Charles Brailey

Belayneh Tafesse

Kenneth Wayne Cash

A system, method and article of manufacture are provided for the automatic recovery from errors encountered during an automated Licensed Internal Code (LIC) update on a storage controller. The present invention functions with a concurrent or nonconcurrent automated LIC update. The automated recovery from many error conditions is transparent to the attached host system and on-site service personnel, resulting an improvement in the LIC update process.

Automated error recovery of a licensed internal code update on a storage controller

A system, method and article of manufacture are provided for the automatic recovery from errors encountered during an automated Licensed Internal Code (LIC) update on a storage controller. The present invention functions with a concurrent or nonconcurrent automated LIC update. The automated recovery from many error conditions is transparent to the attached host system and on-site service personnel, resulting in an improvement in the LIC update process.

A system, method and article of manufacture are provided to perform an automated concurrent licensed internal code (LIC) update and an automated nonconcurrent LIC update on a storage controller. The automated concurrent LIC update is performed on a storage controller by sequentially updating each cluster while maintaining operation of the storage controller. The automated concurrent LIC update allows multiple hosts to continue to access data via the storage controller while the system is actively undergoing the LIC update. The automated nonconcurrent LIC update is performed during the time the storage controller in not operating. The automated nonconcurrent LIC update allows service personnel to perform the update in an efficient and timely manner. When the update has completed, the storage controller becomes available to process data and the system is operating at the latest LIC level.

Automated control of a licensed internal code update on a storage controller

Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.

Error handling between a processor and a system managed by the processor

A recovery system for a power supply. The inventive system includes a first circuit which detects a reapplication of wall power to the power supply and generates a signal in response thereto after an interruption in the output thereof. A second circuit then automatically reactivates the power supply on receipt of the signal without operator intervention. The invention is particularly well suited for systems having multiple power supplies each operating within an associated power boundary. In this case, a first power supply provides power to a first load and a second power supply provides power to a second load. A control circuit is provided in each load. The control circuit is equipped to receive the signal indicating a reapplication of power to a power supply within another power boundary and automatically reactivate the power supply.

Power supply with automatic recovery system

A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage work. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accesseed by an address line failure. The method according to the present invention predicts the effect of an address line failure external to the array modules and internal to a card pair and then tests to see if a failure has occurred. The address test does not declare an address failure until a predetermined number of bit failures on a card is found. The test is valid for single and multiple address line failures. Since only one address bit is changed for each path through the test other failing address lines will not be detected until the path with those failing address bits are tested. Thus, even with multiple address line failure the two addresses that are stored to and fetched from are the only one address bit apart.

Growing community of inventors

Tucson, AZ, United States of America

Jack Harvey Derenburger