Harris Corporation

Intersil Corporation

Intersil Americas Inc.

Fairchild Semiconductor Corporation

Other

Jack H Linn

George V Rouse

James F Buller

Robert K Lowry

William H Speece

Richard W Belcher

Gregory A Schrantz

George S Bajor

John J Hackenberg

Michael G Shlepr

Jun Zeng

Stephen J Gaul

David A Decrosta

Mark A Kwoka

Martin E Walter

William R Wade

Mike M Higley

Anthony L Rivoli

John T Gasner

Rodney S Ridley

Gregg D Croft

Chris A McCarty

John L Benjamin

Linda S Brush

Linda Susan Brush

Frank Stensney

Timothy A Valade

Diana Lynn Hackenberg

Roberta R Nolan-Lobmeyer

Sana Rafie

Elijah Karpov

Katie H Pentas

Mark D Bordelon

Craig S Arruda

Geroge V Rouse

Steven T Slasor

A method of forming a plasma enhanced deposited oxide film on a substrate includes introducing into a chamber containing the substrate silane gas and a dopant gas such as phosphine. The chamber is pressurized and energy is applied to create a plasma. The energy may be a dual frequency energy. The gas rates and pressure are selected to produce a plasma enhanced deposited oxide film on a substrate having a Si&#x2014;O&#x2014;Si bond peak absorbance in the IR spectrum of at least 1092 cm.

Method for forming plasma enhanced deposited, fully oxidized PSG film

A method of making a lead finish incorporating mechanically flattening the plated coating of metal leads. This may be accomplished by mechanical means such as rolling, stamping, peening, coining, forging, or other suitable flattening techniques.

Method of manufacturing a plated electronic termination

A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.

Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone

A silicon-on-insulator integrated circuit comprises a handle die, a substantially continuous and unbroken silicide layer over the handle die, and a substantially continuous and unbroken first dielectric layer overlying one side of the silicide layer. A device silicon layer having an upper surface overlies the first dielectric layer, and a second dielectric layer on the handle die underlies the opposite side of the silicide layer. Interconnected transistors are disposed in and at the upper surface of the device silicon layer. A silicon-on insulator integrated circuit includes a handle die and a first dielectric layer formed on the handle die. A substantially continuous and unbroken silicide layer is formed on the first dielectric layer; the silicide layer has a controlled resistance and provides a diffusion barrier to impurities. A substantially continuous and unbroken second dielectric layer is disposed between the silicide layer and a device silicon layer, and trenches extend through the device silicon layer and silicide layer and separate the device silicon layer into islands, each having an underlying continuous silicide area. Interconnected transistors are disposed in and at an upper surface of the device silicon layer. A bonded wafer integrated circuit comprised a handle die and a homogeneous silicide layer bonded to the handle die. A device layer is bonded to the silicide layer, and interconnected transistors are disposed in and at a surface of device layer.

Bonded wafer with metal silicidation

A process for filling a trench having sidewalls and a floor in a semiconductor device or integrated circuit comprises: forming an insulating layer on the sidewalls and floor of a trench in a semiconductor substrate, substantially filling the trench with semiconductor material, removing semiconductor material from an upper portion of the trench, depositing a first layer of BPSG in the upper portion of the trench, heating the substrate to a first temperature greater than about 850&deg; C. and up to about 1100&deg; C., depositing a second layer of BPSG above the first layer of BPSG, and heating the substrate to a second temperature greater than about 850&deg; C. and up to about 1100&deg; C. The first and second BPSG layers each comprises boron and phosphorus in a weight ratio of boron: phosphorus of greater than 1:1.

Process for depositing and planarizing BPSG for dense trench MOSFET application

A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

Power trench transistor device source region formation using silicon spacer

In a method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits, a surface of a wafer of a monocrystalline semiconductor material is implanted with ions of the semiconductor material a to a selected depth in the wafer to form, adjacent to the surface, an amorphous layer of the semiconductor material. The layer of amorphous semiconductor material extends to a substantially planar zone disposed at substantially the selected depth and comprising the monocrystalline semiconductor material damaged by lattice defects, i.e., end-of-range implant damage. Undamaged material below the selected depth comprises a first layer of the monocrystalline semiconductor material. The wafer is heated under conditions effective to convert the amorphous layer to a second layer of the monocrystalline semiconductor material and to coalesce the zone of damaged monocrystalline semiconductor material, thereby forming a substantially planar intrinsic gettering zone of substantially pure semiconductor material that includes active gettering sites disposed at substantially the selected depth. An insulating bond layer on one surface of a handle wafer is bonded to the surface of the wafer to form a bonded semiconductor-on-insulator substrate comprising a handle wafer, an insulating bond layer, and a device wafer of monocrystalline semiconductor material. The device wafer includes a substantially planar intrinsic gettering zone comprising substantially pure semiconductor material and including active gettering sites. The described bonded substrate is employed in the fabrication of semiconductor devices and integrated circuits.

Method for forming a bonded substrate containing a planar intrinsic gettering zone and substrate formed by said method

An integrated circuit inverted thin film resistor structure and method of manufacture having interconnect defining resistor contacts and leads resident within and coplanar with a supporting layer, resistive material uniformly overlaying the supporting layer and contacts, the resistive material diffused into the resistor/interconnect contact region.

Inverted thin film resistor and method of manufacture

Inverted thin film resistor

Pre heat-treatment processing of a silicon wafer to grow a hydrophilic oxide layer includes an initial step of contacting the wafer with a pre-clean SC-1 bath, thereby producing a silicon wafer surface that is highly particle free. After a deionized water rinse, the wafer is scoured with an aqueous solution containing hydrofluoric acid and hydrochloric acid to remove metallic-containing oxide from the wafer surface. In order to grow a hydrophilic oxide layer, an SC-2 bath (containing hydrogen peroxide and a dilute concentration of metal-scouring HCl) is used. The resulting hydrophilic silicon oxide layer grown on the surface of the silicon wafer using the combined SC-1.fwdarw.HF/HCL.fwdarw.SC-2 wafer cleaning process has a metal concentration no greater than 1.times.10.sup.9. The diffusion length of minority carriers is increased from a range on the order of 500-600 microns to a range on the order of 800-900 microns.

SC-2 based pre-thermal treatment wafer cleaning process

A multilayer microtip probe, and method of manufacture, having a microtip prepared for adhesion of a first overlayer for determining probe operating properties and a hardened protective overlayer for improving resistance to erosion and wear during probe use.

Multilayer microtip probe and method

A gas phase plasma cleaning method is utilized for removing contaminants from the surface of exposed metallic, ceramic and plastic parts on integrated circuits (IC's). A two step method uses a defined gas mixture of argon and oxygen, followed by ammonia and hydrogen. For plastic packages, a two step method using a fluorinated plasma, followed by oxygen and argon is utilized. The gases are separately introduced into a plasma chamber. The argon oxygen mixture is used to remove carbonatious material by chemical reaction and by milling. The ammonia hydrogen mixture is introduced to chemically remove and reduce oxides and phosphates from the metallic parts. The fluorinate is used to remove surface silicon and organo-silicon compounds from the plastic parts, while the oxygen argon mixture removes carbonatious and ionic compounds from the plastic package surface. Surface energies are increased to permit improved adhesion of inks. Additionally, intermediate oxides on the metallic parts formed after the plasma exposure prevent complete regrowth of the normally passivating oxide layer.

Plasma cleaning method for improved ink brand permanency on IC packages

Low temperature wafer bonding using a chemically reacting material between wafers to form a bonded zone to bond two wafers together. Examples include silicon wafers with a silicon-oxidizing bonding liquid which also permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Silicon wafers also may use solid reactants which include deposited layers of metal and polysilicon to form silicide bonded zones. Oxidizers such as nitric acid may be used in the bonding liquid, and a bonding liquid may be used in conjunction with a solid bonding reactant. Dielectric layers on silicon wafers may be used when additional silicon is provided for the bonding reactions. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening and buried resistors.

Bonded wafer processing with oxidative bonding

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Melbourne, FL, United States of America

Jack H Linn