Emc IP Holding Company LLC

United States of America As Represented by the Secretary of the Air Force

Jack Fu

Charles L Woods

Jehad Khoury

Arieh Don

Jaeyoo Jung

Michael J Scharland

Rong Yu

Mark Cronin-Golomb

Ningdong Li

A processing node of a storage system may determine that a host system is implementing a cache-slot aware, round-robin IO distribution algorithm (CA-RR). The processing node may be configured to determine when a sufficient number of sequential IOs will be received to consume a cache slot of the a processing node. If the processing node knows that the host system is implementing CA-RR, then, in response to determining the sufficient number, the processing node may send a communication informing the next processing node about the sequential cache slot hit. If the sequential IO operation(s) are read operation(s), the next processing node may prefetch at least a cache-slot worth of next consecutive data portions. If the sequential IO operation(s) are write operation(s), then the next processing node may request allocation of one or more local cache slots for the forthcoming sequential write operations.

Cache management for sequential IO operations

A host system may be cache-slot aware such that the host system can distribute IOs to processing nodes on a storage system according to cache slot boundaries. A multi-path driver of the host system may determine the cache slot size from one or more communications exchanged with the storage system. The multi-path driver may transition between processing nodes according to slot cache slot boundaries. For IO operations having data portions smaller than the cache slot size, the MP driver may direct multiple IO operations to a same processing node until the collective size of data portions fills a cache slot. For IO operations having a data portion larger than the cache slot, the MP driver may divide the IO operation into sequential IO operations having data portions of a same size as a cache slot, and may transition between processing nodes for each IO operation or a multiple thereof.

Host cache-slot aware 10 management

Maintaining multiple cache areas in a storage device having multiple processors includes loading data from a specific portion of non-volatile storage into a local cache area in response to a specific processor of a first subset of the processors performing a read operation to the specific portion of non-volatile storage, where the local cache area is accessible to the first subset of the processors and is inaccessible to a second subset of the processors that is different than the first subset of the processors and includes loading data from the specific portion of non-volatile storage into a global cache area in response to one of the processors performing a write operation to the specific portion of non-volatile storage, where the global cache area is accessible to the first subset of the processors and to the second subset of the processors. Different processors may be placed on different directors.

Maintaining multiple cache areas

A first lens produces a Fourier transform of the wavefront distorted optical image at the Fourier transform plane. A phase encoded filter is positioned at the transform plane and a second filter is tandemly positioned with respect to the first filter, the second filter having a transmittance which is statistically similar to the reciprocal spatial frequency spectrum of the Fourier transform of the distortion function, to in turn produce an intermediate signal at the transform plane, which is now Fourier transformed by a second lens to recover the optical image having a substantially reduced degree of distortion.

Pseudo deconvolution method of recovering a distorted optical image

Limiting quadratic processing and compansion in photorefractive two beam coupling is disclosed. Two-beam coupling in photorefractive barium titanate employs the imaged intensity of the signal to amplify the reference beam while maintaining the phase of the reference beam. The phase distorted signal beam is converted to that of the controlled phase of the reference beam. The high pump limit of amplification in this two-beam coupling device produces an amplitude compressed output to reduce multiplicative noise. Lost contrast of the image is thereafter restored. Beam clean-up of a non-intelligence bearing beam can be carried out by a similar process; a low pass filter consisting of a pinhole plate can be used in place of the second photorefractive crystal in the Fourier plane and only the planar wavefront portion will pass through the pinhole and may be collimated by a lens to provide a cleaned planar output beam.

Photorefractive limiting quadratic processor

An object beam is passed through an aberrating medium to produce a diffraction distorted image therein, which is imaged upon a spatial light modulator. A probe beam measures the phase aberrated wavefront within the aberrating medium and is used to produce an interference pattern which is employed to produce phase encoding signals to be fed back to the spatial light modulator for compensating in part for the phase distortion of the phase aberrated wavefront. The result is an output image having a substantially reduced degree of distortion.

Growing community of inventors

Brighton, MA, United States of America

Jack Fu