Delco Electronics Corporation

Jack Duane Parrish

Edward H Honnigford

Tracy Adam Noll

An IC voltage clamp and a process for forming the voltage clamp. The voltage clamp includes an MGFO device having an n-type source region, an n-type drain region, and a p-type field implant diffusion between the source and drain regions. The voltage clamp further employs a parasitic NPN device having a collector region coincident with the MGFO drain region, an emitter region coincident with the MGFO source region, and a base region formed by the substrate. A metal gate electrode overlies and is insulated from the field implant diffusion, but electrically connects the source and emitter regions to ground. An input electrode contacts the drain region so as to electrically connect the drain and collector regions to the input voltage of an integrated circuit. The field implant diffusion and drain/collector regions are formed by overlapping their masks, such that a lower breakdown voltage is achieved between the NPN collector and the substrate and field implant diffusion (the NPN base). The voltage clamp is capable of withstanding electrostatic discharge pulses of greater than about 8000 Vdc, and is particularly adapted for use in protecting a CMOS IC that operates at high voltages, such as automotive battery voltages with 40 Vdc transients, without interfering with the operation of the IC.

Growing community of inventors

Round Rock, TX, United States of America

Jack Duane Parrish