Intel Corporation

Jack Doweck

Eliezer Weissmann

Ohad Falik

Ben-Zion Friedman

James B Crossland

Zeev Sperber

Eitan E Rosen

Nicolas I Kacevas

Marina Sherman

Roy Nesher

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Linear to physical address translation with support for page attributes

Apparatus and computing systems associated with data pre-fetching are described. One embodiment includes a processor that includes a first unit to store data corresponding to a load instruction and an instruction pointer (IP) value associated with the load instruction. The processor also includes a second unit to produce a predicted demand address for a next load instruction, the predicted demand address being based on a constant stride value. The processor also includes a third unit to generate an instruction pointer pre-fetch (IPP) request for the predicted demand address. The processor may also include units to arbitrate between generated IP pre-fetch requests and alternative pre-fetch requests.

Pre-fetch apparatus

A computer system having cache modules interconnected in series includes a first and a second cache module directly coupled to an address generating line for parallel lookup of data and data conversion logic coupled between the first cache module and said second cache module.

Dual cache with multiple interconnection operation modes

A processor having an embedded cache memory, the cache including a tag array that is split into first and second halves each having N ways, the first half storing an upper M sets and the second half storing a lower M sets. Lower order linear address bits read the first and second halves in a first phase of a clock cycle. Compare circuitry compares each of the N ways read out of both the first and second halves of the tag array with higher order physical address bits. Select circuitry then selects one of two sets of way select signals based on a higher order linear address bit. A data array having N ways and 2M sets is accessed by the lower order linear address bits in combination with the higher order linear address bit, with the selected set of way select signals outputting data of the correct way.

Embedded cache with way size bigger than page size

A cache memory circuit is disclosed that includes a store hit buffer that buffers write operations to the cache memory circuit and that removes write operations from the critical speed path for the cache memory array. The store hit buffer includes circuitry for determining whether a read operation to the cache memory circuit is targeted for the write operation stored in the store hit buffer and circuitry for merging the write operation from the store hit buffer with the read operation.

Growing community of inventors

Haifa, Israel

Jack Doweck