International Business Machines Corporation

Jack Chris Randolph

Mark Joseph Hickey

Susan Marie Cox

Frederick Jacob Ziegler

Dale John Thomforde

Frank Eliot Levine

Edward Hugh Welbon

Kenichi Tsuchiya

Nathan Samuel Nunamaker

Troy Dale Larsen

William John Starke

Charles P Roth

Chad Balling McBride

John David Irish

Andrew Henry Wottreng

William Thomas Flynn

Robert Neill Newshutz

A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Selection logic enables selecting output of either register bank for input to processor execution logic. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

Digital data processing apparatus having multi-level register file

A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.

Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state

A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

In a first aspect, a stream of data is transmitted by dividing the stream of data into a first substream and a second substream, transmitting the first substream in a first data channel, and transmitting the second substream in a second data channel. Before transmitting the first and second substreams, a first marker signal is inserted in the first substream and/or a second marker signal is inserted in the second substream. A receiver circuit receives the substreams, detects at least one marker signal, and reassembles the data stream from the substreams based on at least one detected marker signal. Numerous other aspects are provided.

Identifying substreams in parallel/serial data link

In a method of communicating a plurality of parallel data packets from a first data parallel bus to a second parallel data bus, each of the plurality of parallel data packets is separated into a first portion and a second portion. Each first portion is converted into a first serial data stream and each second portion is converted into a second serial data stream. The first serial data stream is transmitted over a first serial data channel and the second serial data stream is transmitted over a second serial data channel. The first serial data stream is converted into a plurality of first received portions and the second serial data stream is converted into a plurality of second received portions. Selected first received portions are combined with corresponding selected second received portions so as to regenerate the plurality of parallel data packets.

Data communication method

An apparatus for enabling transmission of parallel data from a first parallel bus to a second parallel bus via a serial data channel includes a first logic element that generates a synchronization character used in a serial data transmission protocol upon detection of a parallel synchronization packet. A serializer converts data from the first logic element into a serial data stream. A de-serializer converts the serial data stream into a plurality of parallel data packets. A second logic element detects the synchronization character and converts the synchronization character into a parallel synchronization packet.

Modification of bus protocol packet for serial data synchronization

A multithreaded processor and a method for performance monitoring within a multithreaded processor are described. According to the present invention, execution circuitry within the multithreaded processor executes instructions in an active thread among first and second concurrent threads, while buffering circuitry buffers instructions and/or data of an inactive one of the first and second concurrent threads. Thread switch logic in the multithreaded processor switches threads by activating the inactive thread and inactivating the active thread. The operation of the multithreaded processor is monitored by a performance monitor, which records occurrences of an event generated by switching threads.

Performance monitoring of thread switch events in a multithreaded

Performance monitoring capabilities are expanded to an entire data processing system so that performance analyses can be made for operations occurring within the entire data processing system and not merely within the processor or any other device containing the performance monitor. Therefore, there is a provision for communicating performance monitor-related signals between the various performance monitors within the various devices and processor within a data processing system.

Performance monitoring in a data processing system

A method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyzes and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace, if the initial architectural state of the system is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained. To this end, an internal performance monitor within the processor system is utilized to generate an output each processor clock cycle which is indicative of the exact number of instructions which were executed during that clock cycle, an indication of whether or not a branch instruction was taken or not taken, an offset for each interrupt vector which has been taken, the number of data cache misses, the number of instruction cache misses, the number of store conditional instructions which were executed and the number of store conditional instructions which failed. This information, in combination with monitored bus traffic may be utilized to efficiently and accurately reconstruct an instruction trace without adversely affecting performance of the system under test.

Method and system for instruction trace reconstruction utilizing

A method and system for performance monitoring within a multithreaded processor are provided. The system includes a processor responsive to instructions within first and second threads and a performance monitor that separately records a first event generated by the processor in response to the first thread and a second event generated by the processor in response to the second thread. In one embodiment, the processor has first and second modes of operation. In this embodiment, when the performance monitor is operating in the first mode, a first counter within the performance monitor increments in response to each occurrence of the first event and a second counter within the performance monitor increments in response to each occurrence of the second event. Alternatively, when the performance monitor is operating in the second mode, the first counter increments in response to each occurrence of the first event and in response to each occurrence of the second event.

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Rochester, MN, United States of America

Jack Chris Randolph