The University of Texas System

Advanced Micro Devices Corporation

Jack C Lee

Mark I Gardner

H Jim Fulford

Han Zhao

Fei Xue

Mark C Gilmer

Deji Akinwande

Ruijing Ge

Xiaohan Wu

The present disclosure provides a 2-dimensional (2D) non-volatile switch (2DNS), with a vertical metal-insulator-metal (MIM) structure that includes a semiconducting monolayer crystalline non-metallic atomic sheet sandwiched between a top metal electrode and a bottom metal electrode. The 2DNS is able to perform stable non-volatile resistance switching, including both unipolar and bipolar switching, with a high ON/OFF ratio, low ON resistance, and low operating voltage. The monolayer atomic sheet may include hexagonal boron nitride (h-BN) or a transition metal dichalcogenide (TMD), such as MoS, MoSe, WS, or WSe. The present disclosure also provides methods for synthesizing a semiconducting monolayer crystalline non-metallic atomic sheet on a target substrate. The monolayer atomic sheet may include h-BN or a TMD, such as MoS, MoSe, WS, or WSe.

Non-volatile resistance switching in monolayer atomic sheets

A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.

Tunnel field-effect transistor (TFET) with lateral oxidation

Tunnel field effect transistor (TFET) with lateral oxidation

A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process.

Vertical III-V nanowire field-effect transistor using nanosphere lithography

A three-dimensional Gate-Wrap-Around Field-Effect Transistor (GWAFET). The GWAFET includes a substrate of III-V semiconductor material. The GWAFET further includes one or more channel layers with a gate wrapped around these one or more channel layers. Additionally, the GWAFET includes a barrier layer residing on the top channel layer with a layer of doped III-V semiconductor material residing on each end of the barrier layer. A source and drain contact are connected to the layer of doped III-V semiconductor material as well as to the multiple channels in the embodiment with the GWAFET including multiple channel layers. By having such a structure, integration density is improved. Furthermore, electrostatic control is improved due to gate coupling, which helps reduce standby power consumption. Furthermore, by using III-V semiconductor material as opposed to silicon, the current drive capacity is improved.

Three-dimensional gate-wrap-around field-effect transistor

A PMOS or CMOS device includes an active region with a shallow heavy atom p-type implant. The PMOS device has a substrate, at least one gate electrode disposed on the substrate, and first and second doped active regions disposed adjacent to the gate electrode. The first active region has a higher concentration of a p-type heavy atom dopant material than the second active region. In one method of forming the PMOS device, spacers are formed on sidewalls of the gate electrode. A first p-type dopant material is selectively implanted into active regions adjacent to the gate electrode using the spacers as a mask. Then a portion of one of the spacers is removed to form a thinner spacer and a second p-type dopant material is selectively implanted into a first one of the active regions using the thinner spacer as a mask. The second p-type dopant material is a heavy atom species.

Semiconductor device with asymmetric PMOS source/drain implant and

A semiconductor device having a gate insulating tri-layer includes a substrate, a nitrogen-containing layer disposed on the substrate, a first dielectric layer disposed over the nitrogen containing layer, a second dielectric layer disposed over the first dielectric layer, and a gate electrode disposed over the second dielectric layer. One of the first and second dielectric layers is formed using an oxide having a dielectric constant ranging from 4 to 100 and the other of the first and second dielectric layers is formed using an oxide having a higher dielectric constant ranging from 10 to 10,000.

Semiconductor device having a tri-layer gate insulating dielectric

A semiconductor device is formed which includes a shallow PMOS active region containing a heavy atom p-type dopant material. In an exemplary process for making a PMOS device or portion of a device, at least one PMOS gate electrode is formed over a PMOS device region of a substrate. A PMOS spacer is formed on a sidewall of a PMOS gate electrode. An amorphizing dopant material is selectively implanted into a PMOS active region using the PMOS spacer as a mask. A heavy atom p-type dopant material is selectively implanted into the PMOS active region using the PMOS spacer as a mask. The order of implantation of the amorphizing dopant material and the heavy atom p-type dopant material may be reversed.

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Austin, TX, United States of America

Jack C Lee