Massachusetts Institute of Technology

USA as Represented by Secretary of the Navy

Dataflow Computer Corporation

Acorn Networks, Inc.

Jack B Dennis

David P Misunas

Sam Brandon Sandbote

Joel Zvi Apisdorf

One embodiment of the present invention prioritizes resource utilization in a multi-thread processor. A priority register stores thread information for P threads. The thread information includes P priority codes corresponding to the P threads, at least one of the P threads requesting use of at least one resource unit. A priority selector generates assignment signal to assign the at least one resource unit to the at least one of the P threads according to the P priority codes.

Prioritizing resource utilization in multi-thread computing system

One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a command message specifying a peripheral operation. A processing slice is coupled to the peripheral bus to execute a plurality of threads. The plurality of threads includes a first thread sending the command message to the peripheral unit.

Multi-thread peripheral processing using dedicated peripheral bus

A system and method process data elements on multiple processing elements. A first processing element processes a task. A second processing element, coupled to the first processing element, is associated with a task. The first processing element sends a critical-section end signal to the second processing element while processing the task at the first processing element. The second processing element resumes the task in response to receiving the critical-section end signal.

System and method for processing overlapping tasks in a programmable network processor environment

A real-time scheduler for scheduling periodic access to a shared resource by a number of channels. The channel period for each channel is represented by a channel value partitioned into an extra-fine value, a fine value, and a coarse value. The fine value is in units of access intervals, the length of time of each access. The coarse value is in units of scheduling periods, the maximum number of access intervals that can be represented by the fine value. The extra-fine value is in units of a number that evenly divides the access interval. During each scheduling period all non-zero coarse values are decremented by one and then if zero, indicate that the next cell send time for that channel falls in the next scheduling period. Concurrently, a fine process executes repeatedly in which all fine values that had a zero coarse value at the end of the previous scheduling period are compared to find the smallest value. The scheduler waits until the smallest value is less than or equal to the current cell interval, and then outputs a trigger signal to initiate the sending of the next cell of the channel and to adjust the channel value using the channel period such that the extra-fine value overflows into the fine value.

Real-time scheduler method and apparatus

In a computer, a machine code program is run by a succession of assignments of groups of replicated code-blocks to groups of memory locations for a succession of executions by groups of processing elements, the code-block replications being determined in relation to data structure definitions and the succession of executions being determined in relation to the succession of assignments.

Method and product involving translation and execution of programs by

This invention provides a novel computer design that is capable of utilizing large numbers of very large scale integrated (VLSI) circuit chips as a basis for efficient high performance computation. This design is a static dataflow architecture of the type in which a plurality of dataflow processing elements communicate externally by means of input/output circuitry, and internally by means of packets sent through a routing network that implements a transmission path from any processing element to any other processing element. This design effects processing element transactions on data according to a distribution of instructions that is at most partially ordered. These instructions correspond to the nodes of a directed graph in which any pair of nodes connected by an arc corresponds to a predecessor-successor pair of instructions. Generally each predecessor instruction has one or more successor instructions, and each successor instruction has one or more predecessor instructions. In accordance with the present invention, these instructions include associations of execution components and enable components identified by instruction indices.

Dataflow processing element, multiprocessor, and processes

A processor is described which achieves highly parallel execution of programs represented in data-flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor incorporates practical data-flow processing of a Fortran-level data-flow language. The processor has a unique architecture which avoids the problems of processor switching and memory/processor interconnection that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.

Data processing apparatus for highly parallel execution of stored

A digital computer may be structured in two separate sections, one of which performs the execution of arithmetic and conditional instructions, and the other which contains and performs operations upon data structures. The organization of the structure processing section of a digital computer is described herein. The structure processing section maintains data structures represented as acyclic directed graphs and is viewed as a functional unit by the instruction processing section; that is, instructions specifying structure operations are sent to the section, and any resulting values are returned to the instruction processing section. The organization of the structure processing section permits the simultaneous processing of many structure operations.

Data processing apparatus for highly parallel execution of data

A processor is described which achieves highly parallel execution of programs represented in data-flow form. The processor operates in a data-driven fashion; that is, an instruction of a program in the processor is enabled for execution upon the arrival of all required operands, and upon being executed, sends copies of the resulting value to all instructions which require it for their execution. The processor incorporates a form of deadlock prevention between the instructions of a data-flow program, allowing a value to be generated by an instruction and sent to the successor instructions in the computation only when those instructions are ready to receive the value. The incorporation of this mechanism prevents the possibility of conflict between successive stages of a pipelined computation and between successive iterations of an iterative computation.

Packet communication is used in the architecture of a memory system capable of processing many independent memory transactions concurrently. The behavior of this memory system is prescribed by a formal memory model appropriate to a computer system for data flow programs.

Packet memory system for processing many independent memory transactions

Packet communication is used in the architecture of a memory system having hierarchical structure. The behavior of this memory system is prescribed by a formal memory model appropriate to a computer system for data flow programs.

Packet memory system with hierarchical structure

This invention is a new concept for the organization of digital data processing apparatus, suitable for highly parallel execution of certain computations involving repeated patterns of computational operations. Possible applications include many types of signal processing computations such as filtering, modulation and waveform generation. The invention permits exploitation of the unique properties of asynchronous digital logic.

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Belmont, MA, United States of America

Jack B Dennis