International Business Machines Corporation

Other

Siemens Aktiengesellschaft

Kabushiki Kaisha Toshiba

Infineon Technologies Ag

Infineon Technologies North America Corp.

Infineon Technologies LLC

Siemens Components, Inc.

Siemens Microelectronics Limited

International Business Machines Coirporation

Qimonda Ag

Jack Allan Mandelman

William R Tonti

Carl John Radens

Ramachandra Divakaruni

Louis Lu-Chen Hsu

Louis L Hsu

Toshiharu Furukawa

Kangguo Cheng

Jeffrey P Gambino

David V Horak

Gary Bela Bronner

Dureseti Chidambarrao

Mark Charles Hakey

Claude Louis Bertin

Ulrike Gruening

Chih-Chao Yang

Herbert Lei Ho

Steven J Holmes

Charles W Koburger, Iii

Roger Allen Booth, Jr

Bruce Bennett Doris

Rajarao Jammy

Oleg Gluschenkov

Haining S Yang

Omer H Dokumaci

Rajiv V Joshi

Louis C Hsu

Thomas W Dyer

Russell J Houghton

Edward J Nowak

Anthony Richard Bonaccio

Erik L Hedberg

Brian Joseph Greene

William Paul Hovis

Reinhard J Stengl

Howard L Kalter

Chun-Yung Sung

Lawrence Alfred Clevenger

Ghavam G Shahidi

Geng Wang

Jochen C Beintner

Devendra K Sadana

Chung H Lam

Robert J Gauthier, Jr

Wayne Frederick Ellis

Wilbur David Pricer

Helmut Horst Tews

Tze-Chiang Chen

John Kenneth DeBrosse

Wagdi William Abadeer

Li-Kong Wang

Byeong Yeol Kim

Tak H Ning

Sebastian Theodore Ventrone

John Atkinson Fifield

Dae-Gyu Park

Johnathan E Faltermeier

Michael D Potter

Michael P Belyansky

Paul Christian Parries

Michael John Hargrove

John Edward Cronin

Steven H Voldman

Son Van Nguyen

Keith Kwong Hon Wong

John Edward Sheets, Ii

James William Adkisson

Kern Rim

Dominic Joseph Schepis

Michael Patrick Chudzik

Jack Oon Chu

Laertis Economikos

Pai-Hung Pan

Chandrasekhar Narayan

Martin Schrems

Norman Jay Rohrer

David Edward Kotecki

K Paul Muller

Huilong Zhu

Daniel C Edelstein

John J Ellis-Monaghan

Kevin K Chan

Terence B Hook

Wendell P Noble

Zhijiong Luo

Timothy Joseph Dalton

Seiki Ogura

Wai-Kin Li

Daniel Paul Kolz

Till Schloesser

John Michael Borkenhagen

Ronald G Filippi

Bomy A Chen

Robert C Wong

Meikei Ieong

James Albert Slinkman

Yun-Yu Wang

Richard Quimby Williams

Wesley Charles Natzle

Kwong Hon Wong

In a first aspect, a first method of manufacturing a high-voltage transistor is provided. The first method includes the steps of (1) providing a substrate including a bulk silicon layer that is below an insulator layer that is below a silicon-on-insulator (SOI) layer; and (2) forming one or more portions of a transistor node including a diffusion region of the transistor in the SOI layer. A portion of the transistor node is adapted to reduce a voltage greater than about 5 V within the transistor to a voltage less than about 3 V. Numerous other aspects are provided.

High-voltage silicon-on-insulator transistors and methods of manufacturing the same

A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.

Layered structure with fuse

A semiconductor device and a method of fabricating a semiconductor device, wherein the method includes forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.

Sea-of-fins structure on a semiconductor substrate and method of fabrication

A field effect transistor (FET) with an adjacent body contact, a SOI IC with circuits including the FETs and a method of fabricating the ICs. Device islands are formed in the silicon surface layer of a SOI wafer. Gates are defined on the wafer. Body contacts are formed in a perimeter conductive region adjacent to the gates. The body contacts may be either a silicide strap along the gate sidewall at one side of the FET or a separate contact separated from the gate by a dielectric stripe at one side of the FET. Separate contacts may be connected to a bias supply.

Silicon on insulator (SOI) field effect transistors (FETs) with adjacent body contacts

Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

Method of fabricating field effect transistors with low k sidewall spacers

Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.

FinFET with reduced gate to fin overlay sensitivity

A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

Structure and method for improving storage latch susceptibility to single event upsets

A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.

Electronic fuses in semiconductor integrated circuits

A system for protecting an electronic device from cosmic rays includes a frame in which the circuit is disposed, a cosmic ray detection circuit and a protection circuit. The cosmic ray detection circuit is supported by the frame and is spaced apart from the circuit. The cosmic ray detection circuit is configured to assert an incoming cosmic ray signal when a cosmic ray interacts with the cosmic ray detection device. The protection circuit is coupled to the incoming cosmic ray signal and is configured to cause the electronic device to enter a protected state when the cosmic ray signal is asserted.

Magnetic induction grid as an early warning mechanism for space based microelectronics

The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as a design structure including the semiconductor memory devices embodied in a machine readable medium. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 &#x3bc;m and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

High-density, trench-based non-volatile random access SONOS memory SOC applications

A semiconductor device and a method of fabricating a semiconductor device is disclosed, the method comprises including: forming etching an oxide layer to form a pattern of parallel oxide bars on a substrate; forming nitride spacers on side walls of the parallel oxide bars, with gaps remaining between adjacent nitride spacers; forming silicon pillars in the gaps; removing the nitride spacers to form a plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film.

A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

Vertical SOI trench SONOS cell

Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure comprises an insulating layer of a dielectric material, an opening having sidewalls extending from a top surface of the insulating layer toward a bottom surface of the insulating layer, and a conductive feature disposed in the opening. The design structure includes a top capping layer disposed on at least a top surface of the conductive feature and a conductive liner layer disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer of the design structure has sidewall portions that project above the top surface of the insulating layer adjacent to the sidewalls of the opening.

Structures incorporating interconnect structures with improved electromigration resistance

Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.

Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering

Growing community of inventors

Flat Rock, NC, United States of America

Jack Allan Mandelman