Avago Technologies General IP (singapore) Pte. Ltd.

Jack Ajoian

Li Sun

Deog-Soon Choi

Nitesh Kumbhat

Hyun-Mo Ku

Lea-Teng Lee

Aaron Lee

Padam Jain

A process for forming an encapsulating mold compound into a molded solder mask on a bottom surface of a PCB is provided that allows the molded solder mask to have a very precise, preselected thickness, or height, while also ensuring that no gaps between the solder mask and side walls of the electrical contact pads exist. A circuit board and circuit board assembly that incorporate the molded solder mask are also provided. The molded solder mask is fabricated in such a way that overlap between the molded solder mask and the electrical contact pads and gaps between the molded solder mask and the side walls of the electrical contact pads are avoided. In addition, the molded solder mask allows the pitch between adjacent electrical contact pads to be greatly reduced compared to the pitch that is possible using a traditional solder mask formed by the traditional photolithographic approach.

Printed circuit board (PCB) and PCB assembly having an encapsulating mold material on a bottom surface thereof and methods for molding an encapsulating mold material on a bottom surface of a PCB

A build-up process for fabricating a multi-layer PCB is provided during which a mezzanine redistribution, or routing, structure is formed within one of the PCB dielectric material layers that allows additional electrical interconnections (i.e., traces and crossovers) to be made within that layer, thereby obviating the need to add an additional PCB layer in order to make those interconnections. The mezzanine redistribution structure also can be interconnected with the metal layers that are above and below it to further increase routing complexity and flexibility. The mezzanine redistribution structure can be formed without increasing the total thickness of the PCB and without substantially increasing costs.

Methods and devices for providing increased routing flexibility in multi-layer printed circuit boards

A build-up process for fabricating a multi-layer PCB is provided that prevents, or at least reduces the lengths of, overhangs in the finishing metal layer that is plated onto the electrical contact metal layer. The metal seed layer is etched away prior to plating the finishing metal layer onto the electrical contact metal layer. The electrical contact metal layer is covered with a layer of dielectric material, which is then patterned to selectively expose preselected areas of the electrical contact metal layer. The exposed preselected areas of the electrical contact metal layer are then plated with the finishing layer of metal. The result is that overhangs are eliminated or at least greatly reduced in length. In addition, the dielectric material layer serves a function similar to that of a solder mask and obviates the need to apply the oxide to serve as a solder mask.

Methods and devices for preventing overhangs in a finishing layer of metal formed on electrical contact surfaces when fabricating multi-layer printed circuit boards

A method is provided for fabricating a substrate having multiple metal layers separated by one or more dielectric layers, respectively. The method includes forming a cavity in at least one dielectric layer through an exposed portion of a top dielectric layer of the substrate, applying metal to side and bottom surfaces of the cavity, forming a pattern through a portion of the metal applied to the bottom surface of the cavity, and micro-etching the metal applied to the bottom surface of the cavity. The micro-etching extends the pattern through a remaining portion of the metal applied to the bottom surface of the cavity.

Growing community of inventors

Campbell, CA, United States of America

Jack Ajoian