Arm Limited

Jacek Wiatrowski

Yew Keong Chong

Gus Wai-Yan Yeung

Martin Jay Kinkade

Amarnath Shanmugam

A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of the column. Precharge circuitry for precharging the output lines to a predetermined voltage, the precharge circuitry comprising a plurality of switching devices corresponding to the plurality of columns each switching device controlled by a data output request signal and a power mode signal. The plurality of switching devices each comprising at least two switches, the at least two switches comprising a data output switch controlled by the data output request signal and a power switch controlled by the power mode signal, the plurality of switching devices connecting the output lines to the predetermined voltage in response to both the power mode signal indicating an operational mode and the data output request signal indicating data is to be output; wherein the power mode switch is configured to have a higher capacitance than the data output switch.

Reducing peak currents required for precharging data lines in memory devices

An integrated circuit memoryincorporates a first array of bit cellsand a second array of bit cellswith word line driver circuitrydisposed therebetween. Word line helper circuitryis disposed at the opposite edges of the arrayto the word line driver circuitry. The helper circuitry is responsive to the word line signal on a word linebeing driven towards an asserted value to switch on and further drive the word line signal towards the asserted value. The helper circuitry is switched off by a global reset signal, which may be a self-timed global reset signal.

Growing community of inventors

Austin, TX, United States of America

Jacek Wiatrowski