Vishay-siliconix

Siliconix Incorporated

Vishay Intertechnology, Inc.

Daimler-benz Ag

Vishay Semiconductor Gmbh

Jacek Korec

Sik Lui

Y Mohammed Kasem

Anup Bhalla

Haim Goldberger

Jack Van Den Heuvel

Harianto Wong

Dorman C Pitzer

Xiaorong Shi

Robert Xu

Richard Kent Williams

Mohamed N Darwish

Wayne Bryan Grabowski

Yueh-Se Ho

Mohammed Kasem

Eddy Tjhia

Heinrich Schlangenotto

Bosco Lan

Alexander Bodensohn

Chang-Sheng Chen

Lee Shawn Luo

Rainer Constapel

Shuming Xu

Shekar S Malikarjunaswamy

Marius Fuellmann

Domon Pitzer

Dorman Pitzer

Robert Q Xu

In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

Trench-gated MIS devices

A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.

Precision high-frequency capacitor formed on semiconductor substrate

A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.

Method of forming self aligned contacts for a power MOSFET

A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.

Structures of and methods of fabricating trench-gated MIS devices

A Schottky rectifier includes a rectifying interface between a semiconductor body and a metal layer. Trenches are formed in the surface of the semiconductor body and regions of a conductivity type opposite to the conductivity type of the body are formed along the sidewalls and bottoms of the trenches, the regions forming PN junctions with the rest of the body. When the rectifier is reverse-biased, the depletion regions along the PN junctions merge to occupy the entire width of the mesas. The device is fabricated by implanting dopant directly through the sidewalls and bottoms of the trenches, by filling the trenches with a material containing dopant and causing the dopant to diffuse through the sidewalls and bottoms of the trenches, or by implanting and diffusing the dopant into a gate filling material.

Method of fabricating trench junction barrier rectifier

In one embodiment of the present invention, a method for fabricating semiconductor devices comprises forming an active region about a front-side of a substrate. A plurality of trenches are then formed about a back-side of the substrate. A grid of banks separates the trenches. A conductive material is then applied to the back-side of the substrate. The trenches and the conductive material act to reduce the on-state resistance of the substrate and enhance thermal conductivity, while the grid of banks maintains the structural strength of the wafer.

Semiconductor substrate with trenches for reducing substrate resistance

Growing community of inventors

San Jose, CA, United States of America

Jacek Korec