Samsung Electronics Co., Ltd.

Ja-hyun Koo

Jeong-ho Bang

Hyun-seop Shim

Jong-bok Tcho

When high speed memory devices are tested using a tester having a lower operating frequency than the operational speed of the memory device, limit conditions for the tester signals are required to prevent the interference between the tester and device signals. The present invention provides the limit conditions for the shift and strobe signal. The strobe signal is delivered to comparators with a delivery delay time defining the dead time zone. The shift signal controls the data path of the device to and from a driver and a comparator. When the strobe signal is within the present test cycle, the shift signal of a read cycle must be activated at the same time or earlier than the activation time of the WE/ signal of the next write cycle and the shift signal of a write cycle must start at the same time or earlier than the activation time of the OE/ signal of the next read cycle. When the strobe signal is outside of the test cycle, the shift signal must meet prescribed maximum and minimum timing conditions.

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Cheonan, South Korea

Ja-hyun Koo