Samsung Electronics Co., Ltd.

Ja-Eung Koo

Bo-un Yoon

Seung-Hoon Choi

Ho-young Kim

Il-Young Yoon

Dong-Chan Kim

Sang-rok Hah

Hong-Seong Son

Man-Geun Cho

Kwan-Sik Kim

Duk-Ho Hong

Seung-Jae Lee

Nae-in Lee

Sang-Hyun Park

Byung-Lyul Park

Jong-Won Lee

Hong-Jae Shin

Kyung-Tae Lee

Chang-Sun Hwang

Sung-Bae Lee

Jae-ouk Choo

Sang-cheol Han

Moo-yong Park

Jun-Hwan Yim

Yeon-Tack Ryu

Yeong-Bong Park

Il-Su Park

Youn-Su Ha

Joo-Cheol Han

No-Ul Kim

Min-Chan Gwak

Jong-Hyung Park

Leian Bartolome

Hyoung-Bin Moon

II-Young Yoon

A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

Semiconductor device and method of manufacturing the same

A semiconductor device may include a gate electrode structure on a first region of a substrate including the first region and a second region, a capping structure covering an upper surface of the gate electrode structure, the capping structure including a capping pattern and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, an alignment key on the second region of the substrate, the alignment key including an insulating material, and a filling structure on the second region of the substrate, the filling structure covering a sidewall of the alignment key, and including a first filling pattern, a second filling pattern covering a lower surface and a sidewall of the first filling pattern and a second etch stop pattern covering a lower surface and a sidewall of the second filling pattern.

Maintaining height of alignment key in semiconductor devices

A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

Methods for fabricating semiconductor device

Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.

Method of manufacturing semiconductor devices

A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

Method of manufacturing semiconductor device

Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

Method of forming the semiconductor device

There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.

Methods of fabricating semiconductor device using sacrificial layer

A flexible membrane for a polishing head and a chemical mechanical polishing (CMP) apparatus having the same are provided. The flexible membrane for a polishing head includes a compressing plate having a first face and a second face opposite to the first face. The first face of the compressing plate holds a substrate with a vacuum provided thereto and compresses the substrate on a polishing pad. The second face of the compressing plate is combined with a supporter of the polishing head. The second face and the supporter define a space to which the vacuum for holding the substrate and a first pneumatic pressure for compressing the substrate are applied. A dividing member combined with the supporter is formed on the second face. The dividing member divides the space into at least two regions. A pneumatic pressure-introducing portion is formed at the dividing member. A second pneumatic pressure is provided to the compressing plate through the pneumatic pressure-introducing portion.

Flexible membrane for a polishing head and chemical mechanical polishing (CMP) apparatus having the same

There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor. Further, instead of the second polishing end point detector, an optical signal polishing end point detector may be employed, for detecting the polishing end point by the light illuminated on the wafer and reflected from the wafer.

Chemical mechanical polishing apparatus

A method of fabricating a semiconductor device is provided. The method includes forming an interconnection line over a ssubstrate. The interconnection line functions as a first electrode. A first insulating layer is formed on the substrate including the metal interconnection line. An electrode layer and an oxide layer are formed on the first insulating layer. A photoresist pattern is formed on the oxide layer. The oxide layer and the electrode layer are etched using the photoresist pattern as an etching mask. As a result, a second electrode and an oxide layer pattern, which are stacked, are formed over the interconnection line. At least the electrode layer is etched using a wet etching technique. The photoresist pattern is then removed.

Method of fabricating a metal-insulator-metal capacitor

Growing community of inventors

Yongin-si, South Korea

Ja-Eung Koo