Hynix Semiconductor Inc.

Skhynix Inc.

Ja Chun Ku

Sang Tae Ahn

Eun Jeong Kim

Hyeon Ju An

Chan Bae Kim

Hyo Seok Lee

Chai O Chung

Sung Kyu Min

Jin Hyock Kim

Kang Sik Choi

Wan Soo Kim

Kwon Hong

Hae Chan Park

Young Ho Lee

Jang Uk Lee

Keun Chul Lee

Se Hun Kang

Seung Beom Baek

A resistive memory device operable with low power consumption and a memory apparatus and data processing system including the same are provided. The resistive memory includes a chalcogenide compound containing 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te).

Resistive memory device and memory apparatus and data processing system having the same

A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially filled with a first insulation layer. An etch protection layer is formed on the surfaces of the trenches that are filled with the first insulation layer. A second insulation layer is filled in the trenches formed with the etch protection layer to form an isolation structure in the isolation regions of the semiconductor substrate. Finally, portions of the active regions of the semiconductor substrate are recessed such that the isolation structure has a height higher than the active regions of the semiconductor substrate.

Method for manufacturing a semiconductor device capable of preventing the decrease of the width of an active region

A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si&#x2014;H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.

Template derivative for forming ultra-low dielectric layer and method of forming ultra-low dielectric layer using the same

A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns.

Method of manufacturing a phase change memory device using a cross patterning technique

A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.

Semiconductor device having resistive device

A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor substrate; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill a trench; first annealing the flowable insulation layer at least three times; second annealing the first annealed flowable insulation layer; removing the second annealed flowable insulation layer until the hard mask pattern is exposed; and removing the exposed hard mask pattern.

Method for forming device isolation structure of semiconductor device using annealing steps to anneal flowable insulation layer

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Gyeonggi-do, South Korea

Ja Chun Ku