Samsung Electronics Co., Ltd.

Ja Bin Lee

Zhe Wu

Jinwoo Lee

Seung-Geun Yu

Kyubong Jung

Jin Woo Lee

Dongho Ahn

Jung Moo Lee

Zhu Wu

Jae Ho Jung

Kwangmin Park

Jeonghee Park

Heeju Shin

Hee Ju Shin

Dong Ho Ahn

Gwangguk An

Jong Uk Kim

Kwang Min Park

Jeong Hee Park

Kyu Bong Jung

Dong Sung Choi

A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.

Semiconductor memory device with selection patterns, storage patterns, and a gap fill layer and method for fabricating the same

A variable resistance memory device includes a plurality of memory cells arranged on a substrate. Each of the memory cells includes a selection element pattern and a variable resistance pattern stacked on the substrate. The selection element pattern includes a first selection element pattern having a chalcogenide material and a second selection element pattern having a metal oxide and coupled to the first selection element pattern.

Variable resistance memory device

A switching element includes a lower barrier electrode on a substrate, a switching pattern on the lower barrier electrode, and an upper barrier electrode on the switching pattern. The lower barrier electrode includes a first lower barrier electrode layer, and a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern and whose density is different from the density of the first lower barrier electrode.

Switching element, variable resistance memory device, and method of manufacturing the switching element

A switching element includes a lower barrier electrode disposed on a substrate, a switching pattern disposed on the lower barrier electrode, and an upper barrier electrode disposed on the switching pattern. The switching pattern includes a first switching pattern, and a second switching pattern disposed on the first switching pattern and having a density different from a density of the first switching pattern.

A memory device includes a word line, a bit line intersecting the word line, and a memory cell at an intersection of the word line and the bit line. The memory cell includes a first electrode connected to the word line; a second electrode connected to the bit line; and a selective element layer between the first electrode and the second electrode. The selective element layer includes one of Ge&#x2014;Se&#x2014;Te, Ge&#x2014;Se&#x2014;Te&#x2014;As, and Ge&#x2014;Se&#x2014;Te&#x2014;As&#x2014;Si, and a composition ratio of arsenic (As) component of each of the Ge&#x2014;Se&#x2014;Te&#x2014;As and the Ge&#x2014;Se&#x2014;Te&#x2014;As&#x2014;Si being greater than 0.01 and less than 0.17.

Memory device, memory cell and method for programming memory cell

There is provided a non-volatile memory device which can enhance the reliability of a memory device by using an ovonic threshold switch (OTS) selection element including a multilayer structure. The non-volatile memory device includes a first electrode and a second electrode spaced apart from each other, a selection element layer between the first electrode and the second electrode, which is closer to the second electrode rather than to the first electrode, and which includes a first chalcogenide layer, a second chalcogenide layer, and a material layer disposed between the first and second chalcogenide layers. The first chalcogenide layer including a first chalcogenide material, and the second chalcogenide layer including a second chalcogenide material. A memory layer between the first electrode and the selection element layer includes a third chalcogenide material which is different from the first and second chalcogenide materials.

Non-volatile memory device

A semiconductor memory device including first lines and second lines overlapping and intersecting each other, variable resistance memory elements disposed at intersections between the first lines and the second lines, and switching elements disposed between the variable resistance memory elements and the first lines. At least one of the switching elements includes first and second chalcogenide compound layers, and conductive nano-dots disposed between the first and second chalcogenide compound layers.

Semiconductor memory device

Growing community of inventors

Hwaseong-si, South Korea

Ja Bin Lee