Micron Technology Incorporated

Round Rock Research, LLC

Boise Technology, Inc.

J Wayne Thompson

Howard Kirsch

Troy A Manning

Todd A Merritt

Jeffrey P Wright

Charles L Ingalls

Victor Wong

Steve V Cole

Toby D Robbs

Benjamin A Millemon

Jim Cullum

George B Raad

Christopher John Kawamura

Brenton P Van Leeuwen

Memory devices are disclosed. A device may include a number of word line drivers, wherein each word line driver of the number of word line drivers including a first transistor and a second transistor. The device may also include a number of first driver gates, wherein the first transistor of each word line driver has a gate coupled to a dedicated first driver gate of the number of driver gates. Further, the device may include a second driver gate coupled to a gate of each second transistor of each of the number of word line drivers. Associated circuits, methods, and systems are also disclosed.

Word line driver circuitry including shared driver gates, and associated methods, devices, and systems

A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.

DRAM sense amplifier active matching fill features for gap equivalence systems and methods

Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.

Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers

A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, but is not within a throat region between two arrays. The location of the row logic allows the throat region to include more bidirectional IO circuitry and signal lines servicing two arrays, which increases the performance of the SDRAM. In addition, separate power bussing is employed for the memory arrays and IO circuitry. This prevents noise from the arrays from affecting the IO circuitry and signal lines of the throat region and vice versa.

Memory architecture

A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

Metal wiring pattern for memory devices

Apparatus and method for a current limiting bleeder device that is shared between columns of different memory arrays and limits a current load on a voltage supply to prevent failure of an otherwise repairable memory device. The memory device includes first and second memory arrays having memory cells arranged in rows and columns where each of the columns of the first and second memory arrays have a equilibration circuit to precharge the respective column. A bleeder device is coupled to a precharge voltage supply and further coupled to at least one equilibration circuit of a column in the first memory array and to at least one equilibration circuit of a column in the second memory array to limit the current drawn by the equilibration circuits from the precharge voltage supply.

Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays

Integrated circuitry includes, a) a first array of electronic devices comprising a series of conductive runners extending outwardly of the memory array with adjacent runners having a device pitch of 0.6 micron or less in a pitch direction, b) a second array of electronic devices peripheral to the first array, the 0.6 pitch conductive runners of the first array extending into the second array, at least some of the conductive runners of the series having respective disjointed gaps therewithin within the second array, the gaps being aligned with one another in the second array, c) a cross running conductor extending substantially parallel with the pitch direction and over the aligned gaps within the second array, d) an insulating dielectric layer provided relative to the disjointed gaps within the second array; and e) a series of electrically conductive plugs provided within the insulating dielectric layer and running substantially perpendicular to the pitch direction within the second array, the conductive plugs respectively extending across the respective gaps between and electrically interconnecting the respective disjointed conductive runners within the second array, the cross running conductor extending elevationally over the conductive plugs. Memory integrated circuitry is also disclosed which incorporates electrically conductive plugs which electrically interconnect disjointed active area regions of different transistors in pitch cells.

Growing community of inventors

Boise, ID, United States of America

J Wayne Thompson