United Microelectronics Corp.

J S Jenq

Chuan-Fu Wang

Der-Yuan Wu

Gary Y Hong

Sun-Chieh Chien

A method of fabricating a self-aligned node contact window starts by forming a bit line on a substrate having a transistor, in which the transistor includes a first source/drain region and a second source/drain region. The bit line is coupled electrically with the first source/drain region of the transistor and there is a cap layer and a first conductive layer formed on the bit line. An insulating layer that is conformal with the bit line, the cap layer and the first conductive layer is formed to serve as an etching stop layer for subsequently forming a conductive spacer. A conductive spacer is formed on the insulating layer of the sidewall of the bit line, the cap layer and the first conductive layer. Using the first conductive layer and the conductive spacer as a mask, an etching process is performed to form a self-aligned node contact window and the second source/drain is thus exposed.

Method and fabricating a self-aligned node contact window

A method for fabricating a cylinder capacitor of a DRAM cell that starts with forming a first oxide layer and then a doped first polysilicon layer on a substrate, patterning the first polysilicon layer to form a first opening that exposes the first oxide layer, forming a polysilicon spacer at the laterals of the first opening. Then, a portion of the first oxide layer is removed to expose the substrate by using the polysilicon spacer and the first polysilicon layer as a mask. A doped second polysilicon layer is formed on the first polysilicon layer and in the first opening. A portion of the second polysilicon layer is removed to form a second opening. A oxide spacer is formed on the laterals of the second opening, and is used as mask to remove a portion of the second polysilicon layer for forming a lower electrode. A dielectric layer and then a third polysilicon layer are formed on the lower electrode after the silicon oxide spacer is removed, wherein the third polysilicon is an upper electrode.

Method for fabricating a cylinder capacitor

A method of forming a DRAM capacitor that utilizes cap layers and spacers to surround the gate and bit line so that the necessary contact openings in a DRAM can be formed in two self-aligned contact processing operations. The capacitor of the DRAM is fabricated by forming contact node and openings within an insulating layer above a substrate, and then forming a first conductive layer conformal to the surface profile of the substrate above the substrate structure. Next, spacers are formed on the sidewalls of the conductive layer, and then a second conductive layer is formed filling the spacer between the spacers and over the substrate structure. Thereafter, a portion of the first conductive layer and the second conductive layer is removed to expose the spacers and the insulating layer. Finally, the spacers and the insulating layer are removed to expose a lower electrode structure that comprises the first and the second conductive layers.

Method of manufacturing dynamic random access memory

The invention provides a method of fabricating a capacitor with high capacitance. A substrate having word lines and bit lines is provided, and a dielectric layer is formed to cover the substrate. A contact window is formed in the dielectric layer to expose an active region. A conductive layer is formed to fill the contact window to connect with the active region. An insulating layer is formed on the conductive layer and the insulating layer and the conductive layer are defined. A hemispherical grained-Si (HSG-Si) layer is then formed on the substrate. An etching process is performed on the HSG-Si layer to expose the dielectric layer using a portion of the insulating layer as a mask. The insulating layer is removed. A storage node with a gear toothed profile is then formed.

Method of fabricating capacitor with high capacitance

A method for manufacturing a DRAM capacitor on a substrate in which an insulator, a first barrier layer, a first conductive layer and a second barrier layer are sequentially applied over the gate electrode and source/drain areas of the substrate. Portions of the deposited layers above the source/drain areas are removed to form trenches which reach these areas. After portions of the second barrier layer and the first conductive layer are etched away, a conductive material layer is deposited thereover, an n-type dopant is doped into the conductive material layer, the dopant is diffused into the substrate to form n.sup.+ -type diffused regions, and the conductive material layer is shaped to form spaced-apart poly spacers and poly fins. Thereafter the first and the second barrier layers are removed to form a bottom plate of the DRAM capacitor which is defined by the first conductive layer, the poly spacers and the poly fins. Finally, a dielectric film is applied over the bottom plate and a further conductive layer is deposited thereover so that it forms a top plate of the DRAM capacitor. The resulting stack/trench capacitor has a larger dielectric film area and a correspondingly larger capacitance.

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Pingtung, Taiwan

J S Jenq