Texas Instruments Corporation

J Patrick Kawamura

David W Evans

James L Krug

Jeffrey E Koelling

Harvey A Vargis

A switching mode converter, having a switching transistor and an inductor, has a discontinuity detector coupled to the inductor which detects when the converter enters the discontinuous mode. The discontinuity detector determines the portion of the cycle of the switching transistor in which the converter is in the discontinuous mode. A feedback controller is coupled to the output of the converter and to the discontinuity detector which alters a feedback control signal of the converter.

DC/DC converter having improved regulation

A DC/DC switching regulator has a semiconductor switch coupled to an inductor, a first capacitor and a rectifier. A circuit to improve the switching efficiency of the semiconductor switch has a transmission gate coupled between the gate of the semiconductor switch and a second capacitor. The transmission gate is turned ON only when the gate of the semiconductor switch is about to make a positive or negative transition and isolated from the first and second voltage sources. A portion of the charge stored in the parasitic capacitance of the gate of the semiconductor switch can be stored in the second capacitor and reused to partially drive the semiconductor switch from the second to the first ON/OFF state. A further embodiment employs this technique with a synchronous rectifier in the regulator circuit.

DC/DC switching regulator having reduced switching loss

Startup operation of a DC/DC switching regulator is controlled by providing a first signal (MAXDC) whose waveform has a duty cycle that varies over time, providing a second signal ( ) indicative of a load condition of the regulator, and combining the first and second signals to produce a third signal ( ). The third signal is used to control a power switch ( ) of the regulator.

Soft-start control for DC/DC switching regulators

A VBB voltage generator unit for biasing of the semiconductor chip substrate is comprised of five basic elements, a standard p-channel substrate pump unit a pump supply voltage switch, a VBB level control logic unit, a high and low frequency oscillators unit, and a Vperi voltage divider unit for generating a fractional Vperi voltage. The substrate pump is a standard two-phase p-channel coupling pump. In response to appropriate control signals, p-channel coupling pump can provide a plurality of VBB voltage levels in response to a single oscillator frequency. The VBB voltage levels can be correlated, via the control signals, to the operational mode of the device.

Apparatus and method for a variable negative substrate bias generator

PLL power up detector includes a capacitor coupled to a charging circuit. The capacitor is charged to a level responsive to the pulse width of the UP and DOWN signals produced by the PFD circuit included in the PLL circuit. When the PLL is near or at the locked state, the UP and DOWN signals will exhibit short high-going pulses or remain at ground level, allowing charger circuit increase the voltage on the capacitor. The Schmitt trigger circuit senses the voltage level on the capacitor and outputs a signal indicating the PLL is near or at the locked state. The Schmitt trigger output signal is coupled to a counter circuit to further validate the lock state of the PLL. The Schmitt trigger output signal must remain at the locked state for n-consecutive reference clock cycles before the PLL power-up signal, is asserted. When the power-up signal is asserted, the charging circuit is disabled and PLL power up detector will not consume quiescent current.

Power-up detector for a phase-locked loop circuit

A memory circuit for operating synchronously with a system clock signal is designed with a memory array (,) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (,) produces a select signal at a respective column select line (,) in response to a first column address signal. A plurality of sense amplifier circuits (,) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (,). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (,) is coupled to receive four data bits from four respective data lines (,) in response to a first cycle of the system clock signal. The data sequence circuit produces four ordered data bits in response to a control signal and a second column address signal. A register circuit (,) is coupled to receive the four ordered data bits. The register circuit produces a sequence of the four ordered data bits in response to a plurality of cycles of the system clock signal after the first cycle of the system clock signal.

Synchronous dynamic random access memory with four-bit data prefetch

A memory circuit for operating synchronously with a system clock signal is designed with a memory array (250, 252, 254, 256) having a plurality of memory cells arranged in rows and columns. Each column decode circuit of a plurality of column decode circuits (502) produces a select signal at a respective column select line (108) in response to a first column address signal. A plurality of sense amplifier circuits (202) is arranged in groups. Each sense amplifier circuit is coupled to a respective column of memory cells. Each sense amplifier circuit includes a select transistor for coupling the sense amplifier to a respective data line (203). A control terminal of each select transistor of a group of sense amplifier circuits is connected to the respective column select line. A data sequence circuit (218) is coupled to receive four data bits from four respective data lines (210, 212, 214, 216) in response to a first cycle of the system clock signal. The data sequence circuit produces four ordered data bits in response to a control signal and a second column address signal. A register circuit (220) is coupled to receive the four ordered data bits. The register circuit produces a sequence of the four ordered data bits in response to a plurality of cycles of the system clock signal after the first cycle of the system clock signal.

A memory circuit (10) provides reduced array sense amplifier circuitry (20, 22) for a memory cell array (24, 26, 28, 30), which has a plurality of memory cells (340) for electrically storing data. A plurality of bitlines (260) are associated with a memory cell array (26) for carrying data to and from the memory cells therein. At least one sense amplifier circuit (16) includes circuitry (332, 334) for addressing selected memory cells via column select lines, and for communicating with an external source of address signals. A local sense amplifier circuit (20, 22) includes circuitry (262, 266) for communicating with the sense amplifier circuit through the selected bitlines. The local sense amplifier circuit also includes circuitry (234, 238) for communicating with other bitlines (232, 236) for addressing other memory cells (28), and further for transmitting data to and from the other memory cells along the selected bitlines, in cooperation with the sense amplifier (16).

Memory circuit including reduced area sense amplifier circuitry

A circuit is designed with a reference circuit (200) for generating a reference signal. The reference signal determines a reference period. A delay circuit (208, 212, 216) responsive to the reference signal produces a delay signal. A control circuit (248, 254, 258, 260, 262) responsive to the delay signal produces a control signal. The delay circuit emulates the speed of an integrated circuit for the reference period. Control signals from the control circuit compensate the integrated circuit performance for measured circuit speed variations.

Integrated circuit with speed detector

A selectable low power signal line (10) is provided that includes a driver circuit (12) connected to receive an input signal for transmission and to receive a mode select signal (SELECT). The driver circuit (12) has a low power mode and a full power mode selectable responsive to the mode select signal (SELECT). The driver circuit (12) is operable, when in the full power mode, to drive an output signal at a full swing of the input signal. When in the low power mode, the driver circuit (12) is operable to drive the output signal at a fraction of the full swing of the input signal. A physical signal line (14) is connected to receive the output signal of the driver circuit (12) and to carry the output signal. A receiver circuit (16) is connected to receive the signal on the physical signal line (14) and is also connected to receive the mode select signal (SELECT). The receiver circuit (16) has a low power and full power mode selectable responsive to the mode select signal (SELECT). The receiver circuit (16) is operable, when in the full power mode, to drive an output signal at a full swing of the signal on the physical signal line (14). When in the low power mode, the receiver circuit (16) is operable to convert the signal on the physical signal line (14) from a fraction of the full swing of the input signal to a full swing of the input signal and to drive the output signal at the full swing.

Selectable low power signal line and method of operation

A memory configuration (20) which includes a first and second bank (B0, B1). Both bank arrays comprises a plurality of wordlines (WLs) and bitlines (BLs). The memory configuration further includes a plurality of column decoder circuits (CDEC0-CDEC7), and a plurality of y-select conductors (C0-C15) generally parallel to the plurality of bitlines of the first bank array. Each of the plurality of y-select conductors is operable to be selected by one of the plurality of column decoder circuits in response to a column address. The memory configuration further includes a plurality of column factor conductors (F0.sub.I, F1.sub.I, F2.sub.I) formed in a direct periphery area existing between the first and second bank arrays. Still further, the memory configuration includes a power conductor (PDD.sub.I) formed between the first and second bank arrays, and aligned generally parallel to the plurality of wordlines of the first and second bank arrays. Lastly, the memory configuration includes a plurality of programmable conductors (PC0-PC7) disposed between and generally parallel to the plurality of y-select conductors. The programmable conductors are formed such that a first portion of each of the plurality of programmable conductors overlies the first bank array and a second portion of each of the plurality of programmable conductors extends toward the direct periphery. Each of the plurality of programmable conductors may be selected for connecting to a corresponding one of the plurality of column factor conductors or to the power conductor.

Multiple bank memory with over-the-array conductors programmable for

An oscillator circuit (150) is designed with a reference circuit (102), responsive to a first voltage, for producing a second voltage. An oscillator (108), responsive to the second voltage, produces a first output signal having a magnitude less than a magnitude of the first voltage. A level translator (114), responsive to the first output signal, produces a second output signal having a magnitude greater than the magnitude of the first output signal. Since the oscillator produces the first output signal with a magnitude less than the magnitude of the first voltage, power consumption is reduced with respect to an oscillator operating at the first voltage. The magnitude of the first output signal is increased by the level translator to a desired magnitude of the second output signal.

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Richardson, TX, United States of America

J Patrick Kawamura