Hewlett-packard Company

Hewlett-packard Development Company, L.P.

J Michael Hill

Jonathan E Lachman

Todd W Mellinger

Jay E Fleischman

Warren Kurt Howlett

Donald R Weiss

Karl P Brummel

Robert McFarland

Brian William Hughes

Jeffery C Brauch

William J Queen

David Thomas Newsome

Jim Dale Peterson

System and method of testing a packaged random access memory (RAM) redundant integrated circuit die comprising: identifying a failed element in the redundant RAM of the packaged integrated circuit die; and replacing the failed element with a redundant element in the redundant RAM of the packaged integrated circuit die.

Method and system for testing RAM redundant integrated circuits

A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width determined by the number of columns of the array, comprises the steps of: writing test data words in parallel to the rows of the plurality of memory blocks; reading out test data words in parallel from the rows of the plurality of memory blocks to a corresponding plurality of on-chip data word comparators; presenting corresponding expected data words in parallel to the plurality of on-chip data word comparators for comparison with the read out data words of the corresponding memory blocks; concurrently comparing corresponding data bits of the read out data words and expected data words in corresponding data bit comparators to generate a column status bit for each data bit comparison; latching the column status bit of a mismatch bit comparison in the corresponding data word comparator; and reading the column status bits of each on-chip data word comparator.

System and method of testing a plurality of memory blocks of an integrated circuit in parallel

The present invention is directed to a system and method which manages one or more errors in a plurality of elements. The invention tests an element of the plurality of elements and detects the error in one of the elements. The invention then repairs a group of N elements, wherein N is greater than one and the group of N elements includes the element with the error. The invention inhibits subsequent repairs of the group of N elements.

Device to inhibit duplicate cache repairs

The invention provides a circuit and method for obtaining a fully functional microprocessor using only a fraction of the available on-chip cache. The memory sub-arrays of the on-chip cache are tested to determine which sub-arrays are functional. After determining which sub-arrays are functional, a set of sub-arrays is selected that constitute a binary fraction of the cache. The CPU is initialized to accommodate a smaller address space corresponding to the size of the selected sub-arrays. Finally, a group of signals are programmed to allow the CPU access to the selected sub-arrays.

Method and apparatus for achieving higher product yields by using fractional portions of imbedded memory arrays

An embodiment of the invention provides a circuit for reducing power in memory cells. The input of the circuit is connected to the wordline of the memory cells. When the wordline is active, the output of the circuit applies a voltage near VDD to the positive voltage supply node of the memory cells. When the wordline is inactive, the output of the circuit applies a voltage that is reduced by at least one Vfrom VDD to the positive voltage supply node of the memory cells.

System and method for reducing leakage in memory cells using wordline control

An edge-triggered, self-resetting pulse generator where a pulse is initiated by a voltage transition and is reset using feedback from the output. A voltage transition is presented at one input of a two-input NOR gate and at the input of a circuit with three inverters in series. The output from the circuit with three inverters in series connects to the second input of the two-input NOR gate. This combination creates a voltage pulse that drives a transfer FET. The transfer FET creates a voltage on a latch. The latch stores the voltage presented on the input and then drives a delay-chain with an odd number of inverters. The output of the delay-chain drives a second transfer FET that resets the latch.

Edge-triggered, self-resetting pulse generator

A highly flexible and complex BIST engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BIST engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.

Flexible and programmable BIST engine for on-chip memory array testing and characterization

A circuit and method characterizes a sense amplifier, such as the type utilized in computer memory systems. The sense amplifier characterization circuit comprises a sense amplifier having one or more inputs and an output, a BIT line connected to one of the one or more inputs of the sense amplifier, a register connected to the output of the sense amplifier; and control logic connected to the BIT line. Optionally, the register is further connected to the control logic, and the register is a scan register connectable to a tester. Preferably, the sense amplifier is a differential sense amplifier, and the circuit further comprises a complement BIT line connected to one of the one or more inputs of the sense amplifier. The method produces one or more signals like an output of a memory cell, operates one or more sense amplifier to produce one or more output states on the basis of the one or more signals, and records the one or more output states. Optionally, the method also records data related to the one or more signals. In one mode of operation, the method sets a voltage of the one or more signals like an output of a memory cell to be a static value during the operating step. In another mode of operation, the method sets a voltage of the one or more signals like an output of a memory cell to be alternating values during the operating step. The method further determines, on the basis of the one or more output states, whether the sense amplifier is acceptable, and if acceptable, the sense amplifier is utilized in a memory system.

Characterization of sense amplifiers

A content addressable memory, CAM, cell wherein the only compare-transfer FETS used are NFETs. The gates of the NFET compare-transfer FETS are driven to a voltage above the positive power supply, VDD. By precharging the bitlines to the negative power supply voltage, GND, the gate of one of the compare-transfer NFETS is driven above VDD when a bitline transitions from a &ldquo;low&rdquo; value to a &ldquo;high&rdquo; value. The capacitance between the bitline being driven high and the gate of a compare-transfer NFET couples the gate higher than VDD. This bootstrapping technique improves the compare access time of a CAM. In addition, this technique reduces the capacitance on the bitlines resulting in faster read and write access times and reduces the physical size of the CAM.

Content addressable memory cell with a bootstrap improved compare

A decoder circuit in a memory system accepts as inputs a clock signal and a plurality of address lines and produces as outputs a plurality of decode lines, such as word lines. The decoder circuit comprises a plurality of pre-decoding circuits, a plurality of latches, and a plurality of AND gates. Each pre-decoding circuit is connected to the clock signal and a unique combination of a subset of the plurality of address lines and their complements. Each pre-decoding circuit produces an output that is set in response to a unique state of the respective subset of the plurality of address lines. Each latch input is connected to an output of a respective one of the plurality of pre-decoding circuits. Each latch output is connected to an AND gate input, and each AND gate output is one of the plurality of decode lines. In another sense, the decoder comprises one or more stages of decoding logic and a set of latches. A first stage of decoding logic accepts the decoder inputs. The outputs of each non-final stage is an input to a subsequent stage. The set of latches are connected to the outputs of a particular non-final stage. A method for using the decoder processes a set of input signals, whereby a set of processed signals are generated. The method latches the processed signals. The latched signals are intermediate signals in a decoding operation, and the method further processes the intermediate signals so as to complete the decoding operation.

Address decoder and method for ITS accelerated stress testing

A novel method and apparatus for automatically programming a redundancy map for a circuit is presented. A circuit comprising a plurality of identical reconfigurable circuit elements and a redundant circuit element includes a redundancy map register which may be programmed to allow faulty circuit elements to be deactivated and bypassed and the redundant circuit element to be activated. A fault detector tests the circuit to generate a fault indicator indicating which one of the reconfigurable circuit elements is a faulty circuit element. An encoder encodes the fault indicator into an encoded fault indicator. A decoder decodes the encoded fault indicator to generate a redundancy map for configuring the reconfigurable circuit elements.

Method for automatically programming a redundancy map for a redundant

An improved random access memory (RAM) system enhances the speed and reduces power dissipation and logic complexity associated with a RAM. The RAM system includes first and second pluralities of RAM cell columns. Each of the columns includes (1) at least one RAM cell, each RAM cell configured to read and write a respective logic state and (2) bit and nbit connections (differential and complimentary) connected to each of the RAM cells. A first multiplexer is designed to multiplex the bit and nbit connections of the first plurality of RAM cell columns. A second multiplexer is configured to multiplex the bit and nbit connections of the second plurality of columns. Decode logic controls the first and second multiplexers, and the decode logic accesses a particular column and cell in one of the first and second pluralities during each memory access. A sense amplifier is configured to read the bit and nbit connections of the first and second pluralities via respectively the first and second multiplexers. The sense amplifier is designed to output a logic state from any of the cells based upon a voltage differential and a polarity between the bit and nbit connections of any of the columns. A write driver is configured to write the bit and nbit connections of the first and second plurality via respectively the first and second multiplexers. The write driver drives a logic state onto any of the cells based upon the voltage differential and the polarity between the bit and nbit connections of any of the columns.

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Fort Collins, CO, United States of America

J Michael Hill