Micron Technology Incorporated

Hewlett-packard Development Company, L.p.

Microsoft Technology Licensing, LLC

Convey Computer

Hewlett-packard Company

Hewlett-packard Corporation

J Michael Andrewartha

Tony M Brewer

Michael K Dugan

William D O'Leary

Eric C Peterson

Richard A Schumacher

Brent A Boudreaux

Martha G Peterson

Farrukh S Syed

John Joseph Siegler

Mark Santaniello

Laura Marie Caulfield

Kirankumar Chhaganlal Patel

Terrell Magee

Bryan David Kelly

Lee Thomas VanLanen

Sriram Govindan

Badriddine Khessib

David R Maciorowski

Edward A Cross

Michael Jay Zalta

Jeffrey Todd Haselby

Scott Stuart Smith

Mark A Shaw

Patrick Wesley Clark

Donald H Friedberg

James A Hess

Bryan Wayne Pogor

Mark Alan Santaniello

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Multiple data channel memory module architecture

The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails.

Testing storage device power circuitry

A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots.

Configurable volatile memory without a dedicated power source for detecting a data save trigger condition

The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.

A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access). A memory interleave system is provided to optimize the interleaving across the system's memory banks to minimize hot spots resulting from the cache-block oriented and non-cache-block oriented accesses of the heterogeneous computing system.

Memory interleave for heterogeneous computing

One embodiment of a non-volatile memory system comprises block-accessible non-volatile memory, random access memory arranged to be linearly addressable by a processor as part of the processor's memory address space, to be read from and written to by the processor, and logic interposed between the block-accessible non-volatile memory and the random access memory and arranged to write parts of the content of the random access memory in blocks to blocks of the non-volatile, block-accessible memory. The logic is arranged to monitor processor writes to the random access memory, and to write blocks of the random access memory that differ from a most recent copy in the non-volatile, block-accessible memory to the non-volatile, block-accessible memory.

Non-volatile storage for backing up volatile storage

The input/output expansion system (&ldquo;I/O expansion system&rdquo;) for an external or main computing unit includes a rack; at least one I/O expansion module mounted to the rack, the I/O expansion module comprising at least one I/O circuit card; a utilities control module mounted to the rack, the utilities control module being configured to receive a command from the external computer unit and generating a signal in response to the command for distribution to at least one I/O expansion module; and expansion power chassis mounted to the rack, the an expansion power chassis being electrically connected to a power source and being configured to distribute the power to the at least one I/O expansion module and the utilities control module.

Modular input/output expansion system for an external computer

The invention provides EMI cable shield termination apparatus. The apparatus includes (a) a cable exit panel coupled to a first electronic system and (b) one or more clamps coupled to the exit panel. The exit panel serves as an interface for one or more cables coupled to the first electronic system; the clamps provide mechanical coupling, and EMI shielding, for the cables to that interface. The exit panel couples to electrical ground such as through connection to the chassis of the first electronic system. The clamps also couple to ground through connection with the exit panel. Preferably, one end of the cables attaches to the clamps, at the interface formed by the exit panel, and the other end of the cables attach to respective ferrules coupled to a second electronics system. Beneficially, the apparatus reduces EMI effects generated from the first electronic system and coupled into the second electronic system. In preferred aspects of the invention, the first and second electronic systems are computers; and each of the clamps forms at least one aperture (&ldquo;clamp aperture&rdquo;) to affix to a cable coupled to the first electronic system. The invention facilitates configurable cable shield terminations to meet mechanical requirements of a given installation; that is, a single cable construction permits multiple optional clamp attachment locations to accommodate different separations of the attached equipment.

Cable shield termination system using clamps and ferrules

A shielded cable assembly contains one or more hardpoints that resist damage arising from possible collapse of the shielded cable assembly under strong compressional forces that are exerted by a clamp assembly in the form of a separable block having first and second opposed members. The hardpoint contains a conduit that protects a data transfer line or cable bundle by compressing electromagnetic shielding between the conduit and the clamp assembly. Cable electromagnetic shielding may be exposed over a selected hardpoint for use as needed in a particular application.

Shielded cable system for high speed cable termination

Growing community of inventors

Woodinville, WA, United States of America

J Michael Andrewartha