Harris Corporation

J G Dooley

David W Hall

Arecio A Hernandez

A partitioned constant delay logic network 208 has a number of constant delay logic elements. The delay of each logic element is held constant by applying a controlled bias voltage, V.sub.bias. The source of the controlled bias voltage is a phase locked loop 201 which has a voltage controlled oscillator 203 constructed out of an odd plurality of constant delay logic elements.

Constant delay logic circuits and methods

A low noise logic (LNL) family is disclosed. An inverter 10 has a pair of load devices NL1, NL2 coupled to the drains of NMOS transistors N 1, N2. The input signal is coupled to the gate of N 1. The drain of N 1 is coupled to the gate of N2. A constant current source 12 is coupled between V.sub.ss and the sources of the transistors N1,N2. Trickle current devices NTR1, NTR2 are coupled to the drains of N 1, N2, respectively to insure input control of the output states. A high logic signal on the gate of N1 steers the constant current to the load NL1 and turns NL2 off. A low logic signal on the gate of N1 turns N1 off and applies a high voltage to the gate of N2, turning N2 on. N2 steers the constant current to NL2.

Growing community of inventors

Melbourne, FL, United States of America

J G Dooley