Samsung Semiconductor Inc.

J Eric Ruetz

A programmable output driver circuit is provided having multiple drive capabilities for optimising noise margins at different frequencies. Several signal paths are designed in parallel, each comprising a driver unit made up of a pull-down and a pull-up transistor. Some of the paths can be disabled by NAND gates slowing down the driver circuit to reduce the attendant noise at lower frequencies. Different types of parallel structures can be designed, allowing for variable rise and fall times of the output signal, as well as skewed duty cycles.

Programmable output drive circuit

A crystal oscillator circuit has a sleep mode of operation that reduces power consumption while maintaining oscillation to provide for a fast transition to a normal mode of operation.

Low-power crystal circuit

A charge pump having gate control voltages multiplexed to gates of FET driver circuits to precisely control charge injected by the charge pump to a low pass filter network. Large capacitors between the supply voltages and the respective gate control voltage derived from the particular supply voltage provide greater noise immunity which further reduces phase errors introduced by injected charge variations. The large capacitors help to hold the gate voltages constant, further controlling the injected charge.

Gate multiplexed low noise charge pump

A start-up circuit for a bias generating circuit includes a current source for providing a small charging current, and transistors for coupling the charging current to the bias generating circuit during power up to force the bias generating circuit into a steady-current state. The start-up circuit also uncouples the current source from the bias circuit after the bias generating circuit is forced into the steady-current state to prevent the charging current from affecting the operation of the bias generating circuit.

Bias start-up circuit

An improved crystal oscillator and output circuit is disclosed. The oscillator has a normal operating mode and a low-power mode. In the low-power mode, a reduced current which is sufficient to maintain oscillation is supplied to the oscillator and the output circuit is disabled. The oscillator can subsequently be returned to normal mode and the output circuit enabled. Since the oscillator is never shut completely off, the time required to resume normal mode oscillations is reduced.

Low-power crystal oscillator

A high-frequency voltage controlled oscillator includes a start-up circuit for preventing the oscillator from enering a stable state and that does not increase the fixed delays in the oscillator feedback paths. A sleep mode feature shuts down the oscillator to conserve power and capacitors are used to isolate the oscillator from high-frequency noise coupled through the power supply inputs.

High frequency VCO circuit

A programmable output driver circuit is provided having multiple drive capabilities for optimizing noise margins at different frequencies. Several signal paths are designed in parallel, each comprising a driver unit made up of a pull-down and a pull-up transistor. Some of the paths can be disabled by NAND gates slowing down the driver circuit to reduce the attendant noise at lower frequencies. Different types of parallel structures can be designed, allowing for variable rise and fall times of the output signal, as well as skewed duty cycles.

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San Bruno, CA, United States of America

J Eric Ruetz