International Business Machines Corporation

Globalfoundries Inc.

J Campbell Scott

Ahmet Serkan Ozcan

Xiao Hu Liu

Chung Woh Lai

Anita Madan

Klaus W Schwarz

Arvind Kumar

Lawrence Shungwei Mok

Wayne Isami Imaino

James Douglas Warnock

Louis C Hsu

Gregory Gower Freeman

Howard Hao Chen

Siyuranga O Koswatta

Daniel J Poindexter

Gregory John Uhlmann

Leon Jacob Sigal

Paul Stephen McLaughlin

Charles Edwin Cox

Pritish Narayanan

Harald Huels

Winfried W Wilcke

Scott Taylor

Feedback within hierarchical neural networks such as hierarchical temporal memories is provided. In various embodiments, a plurality of input streams is received at a first region of a hierarchical artificial neural network. The plurality of input streams is pooled in the first region. One or more recurrent features are identified in the pooled input streams in the first region. A temporal pattern is recognized in the one or more recurrent features in the first region. An indication of the temporal pattern is provided to at least a second region of the hierarchical neural network. A response to a further input is modulated based on feedback from the second region and at least one additional region.

Computational method for feedback in a hierarchical neural network

A computational method is disclosed for the simulation of a hierarchical artificial neural network (ANN), wherein a single correlator pools, during a single time-step, two or more consecutive feed-forward inputs from previously predicted and now active neurons of one or more lower levels.

Computational method for temporal pooling and correlation

Embodiments of the present invention describe a hierarchical cortical emulation using a scratchpad memory device and a storage class memory device. The scratchpad memory device is partitioned into a first subset of memory locations and a second subset of memory locations. A processor from a neural network device is assigned a first memory portion from the first subset, a second memory portion from the second subset, and a third memory portion from the storage class memory device. Further the neural network device and a memory controller perform a compute cycle for a hierarchical level k, 1&#x2264;k&#x2264;n, n being total number of levels. A compute cycle includes performing, by the processor, computations from the level k using neuron data stored in the first memory portion, and in parallel, copying by the memory controller, the neuron data for a hierarchical level k+1 from the third memory portion to the second memory portion.

Virtualization in hierarchical cortical emulation frameworks

Homeostasis-maintaining binary neural networks such as hierarchical temporal memories are provided. In various embodiments, a region of an artificial neural network is initialized. The region comprises a plurality of neurons and has a permanence value associated with each potential synaptic connection between neurons. The initialization comprises connecting a subset of the potential synaptic connections by synapses. A plurality of time-ordered inputs to the region is received. Some of the plurality of neurons are thereby caused to fire upon receipt of each time-ordered input. Upon receipt of each time-ordered input, for each potential synaptic connection between neurons, the permanence value is adjusted according to a firing sequence of the plurality of neurons. Those potential synaptic connections having a permanence value above a predetermined permanence threshold are connected when the total number of connected synapses in the region does not exceed a predetermined connectivity threshold. Synapses whose associated pre-synaptic neuron or post-synaptic neuron have more than a predetermined number of connected synapses are disconnected.

Approaching homeostasis in a binary neural network

Self-adjusting thresholds for synaptic activity in neural networks are provided. In various embodiments, for each of a plurality of neurons within an artificial neural network, an overlap value is determined corresponding to active inputs connected to the neuron via synapses having non-zero synaptic weights. A count of those of the plurality of neurons whose overlap exceeds an activation threshold of the neural network is determined. The count is compared to a predetermined neuronal activity target. The activation threshold of the neural network is adjusted to approach the predetermined neuronal activity target.

Self-adjusting threshold for synaptic activity in neural networks

Three-dimensional (3D) neuromorphic computing systems are provided. A system includes a logic wafer having a plurality of processors. The system further includes a double-sided interposer bonded to the logic wafer and incorporating a signal port ring for sending and receiving signals. The system also includes a plurality of 3D memory modules bonded to the double-sided interposer. The double-sided interposer is a wafer scale or a panel scale providing communication between the plurality of processors and the plurality of 3D memory modules.

High memory bandwidth neuromorphic computing system

A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.

On-chip sensor for monitoring active circuits on integrated circuit (IC) chips

An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.

Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications

A method for manipulating dislocations from a semiconductor device includes directing a light-emitting beam locally onto a surface portion of a semiconductor body that includes active regions of the semiconductor device and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam. Manipulating the plurality of dislocations includes directly scanning the plurality of dislocations with the light-emitting beam to manipulate a location of each of the plurality of dislocations on the surface portion of the semiconductor body by adjusting a temperature of the surface portion of the semiconductor body corresponding to the plurality of dislocations and adjusting a scan speed of the a light-emitting beam.

Dislocation engineering using a scanned laser

A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam.

A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions.

A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.

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Los Gatos, CA, United States of America

J Campbell Scott