Advanced Micro Devices Corporation

J Andrew Lambrecht

Alfred C Hartmann

Scott E Swanstrom

Gary Michael Godfrey

Drew Jon Dutton

Brian C Barnes

Gary M Godrey

A system and method that operate on data in a communication system. The system comprises a communication network for routing objects that include data and a tag and comprised of processing modules for processing the data included in the objects and routing nodes that are operable to route the objects between the processing modules. Each processing module includes a processing memory for storing objects. Each routing node includes a routing memory for storing memory objects and is operable to route objects throughout the system. The objects include stored objects stored in various ones of the respective processing memories and the respective routing memories. Each stored object further includes methods that are executable to perform operations on the data and a processing list that lists the methods to be executed on the data. Each processing node interrogates objects to examine the processing list and execute methods identified by the processing list to perform corresponding operations on the data. The method routes objects in the communication system.

Object oriented on-chip messaging

A computer chip including a data transfer network which comprises a plurality of communications links for transmitting data, a plurality of communication nodes, and a plurality of modules. Each of the communication nodes is directly connected to two or more other communication nodes through respective ones of the communications links. Each communication node is operable to communicate data over the respective one of the communications links. Each module is coupled to at least one of the communication nodes, and the modules are operable to communicate with each other through the communication nodes. The communication nodes are operable to create dynamic routes for the data transferred between any two or more of the plurality of modules over the respective ones of the communications links. The communication nodes form the dynamic routes controlled by a network configuration manager.

Scalable mesh architecture with reconfigurable paths for an on-chip data transfer network incorporating a network configuration manager

A noise environment is sampled via microphone. A processor generates a cancellation signal to offset the effects of the noise to a listener. The cancellation signal is converted into a sample signal compatible with a synthesizer. The synthesizer adjusts the pitch, amplitude and timing of a sample of a patch set to create a substantially continuous output cancellation signal. The continuous output cancellation signal is output via a speaker. The output cancellation signal combines with the noise environment to reduce the effects of the noise environment on the listener. Alternatively, in previously characterized noise environments, one or more cancellation signals may be stored in processor. The processor receives a user input selecting the appropriate cancellation signal and adjusting the parameters of the cancellation signal. After the processor has calculated or selected the cancellation signal and transferred the sampled signal to the synthesizer, the processor is no longer involved in the generation of the cancellation signal. Therefore, the noise cancellation function requires relatively little processing power and is accomplished without the need for special purpose hardware.

Waveform playback device for active noise cancellation

A computer chip including a data transfer network which comprises a plurality of communications links for transmitting data, a plurality of communication nodes, and a plurality of modules. Each of the communication nodes is directly connected to two or more other communication nodes through respective ones of the communications links. Each communication node is operable to communicate data over the respective one of the communications links. Each module is coupled to at least one of the communication nodes, and the modules are operable to communicate with each other through the communication nodes. The communication nodes are operable to create dynamic routes for the data transferred between any two or more of the plurality of modules over the respective ones of the communications links. The communication nodes form the dynamic routes based on statistical data on previous transmissions between the modules. Each communication node may include respective configuration logic for dynamically configuring the dynamic routes, and each configuration logic may include a memory for storing the statistical data on previous transmissions that passed through the respective communications node. The data transfer network may also comprise a routing module for controlling the dynamic routes based on statistical data. The routing module couples to each communication node and monitors the configuration logic. When present and functioning, the routing module adapts the dynamic routes based on an analysis of the statistical data. The statistical data includes one or more of the following for each respective transmission: priority, source module, destination module, number of data units, elapsed transfer time or minimum required transfer time, and total number of transmissions which pass through a given communications node.

Dynamically configured on-chip communications paths based on statistical analysis

A microprocessor including a context save unit is provided. The context save unit is configured to periodically perform context saves. When the microprocessor receives an interrupt signal, the microprocessor enters the interrupt service routine without performing a context save. After completing execution of the interrupt service routine, the microprocessor restores the most recently saved context and begins executing the task at that saved context. The interrupt service routine is entered rapidly but the interrupt service routine does not include instructions for saving the registers which it utilizes to perform its function. The context save unit is configured to perform a context save at the occurrence of a variety of events. A fixed or variable time interval may be selected, and each interval includes several options.

Microprocessor having a context save unit for saving context independent from interrupt requests

A head related transfer function (HRTF) is used to simulate positional three-dimensional sound. The HRTF accounts for the frequency response, delays and reflections of the human body. The HRTF is unique to each individual and is affected by the shape and size of the head, the shape and size of the pinnae, the characteristics of the ear canal and the relationships of the shoulder to the ear. An HRTF for an individual is interactively approximated by first choosing a generalized HRTF. A computer, or other device, outputs audio signals from fixed locations using the generalized HRTF. Although the sound is output from fixed positions, a user may be expected to perceive the sound from a position different than the fixed position from which the sound is output. The user inputs the actual perceived position of the sound to the computer. The computer calculates positional errors between the expected perceived position of the sound and the actual perceived position of the sound. The positional errors are used to either adjust the parameters of the current HRTF or select a new HRTF. The above process is repeated with an adjusted or new HRTF until the positional errors of the HRTF are within an acceptable range of error.

System and method for interactive approximation of a head transfer function

A chip chassis comprises a housing for enclosing a plurality of semiconductor devices having electrical contacts. The housing is configured to include a plurality of slots each adapted for receiving a semiconductor device. The housing further comprises a plurality of connectors in each of the slots. Each connector within a respective slot of the housing is adapted to electrically contact corresponding electrical contacts of the semiconductor device when the semiconductor device is inserted within the respective slot. Each of the plurality of connectors in each of the slots is electrically coupled to provide an electrical backplane within the housing for electrical communications between each of the slots. The housing may be configured to couple thermally with a heat sink and provide access for a flow-through of a forced coolant. The slots may be adapted to receive a particular type of semiconductor device. Moreover, the connectors comprised in a particular slot may be configured for electrically contacting corresponding electrical contacts on the particular type of semiconductor device designed for the corresponding slot when that particular type of semiconductor device is inserted within the slot. The particular types of semiconductor devices which may be housed in the chip chassis include processors, memories, or I/O control modules. Some slots may be configured for the semiconductor devices to access external data storage devices for the storage and retrieval of data. The chip chassis may also include one or more of the semiconductor devices configured to be housed in the slots of the housing.

Chip chassis including a micro-backplane for receiving and connecting a

A computer chip includes a data transfer network. The data transfer network comprises a backbone bus, a plurality of communication ports and a plurality of devices or modules each coupled to the backbone bus. Each of the devices includes or is coupled to one or more communication ports. Some of communication ports are operable to transmit and receive data on the backbone bus. Furthermore, the communication ports are interconnected in a ring topology forming a circular bus or a semi-circular bus. A subset of the communication ports may transmit and receive data on the circular bus or semi-circular bus. For the semi-circular bus, the communication ports are not coupled to form a complete ring topology. The communication ports may be operable to communicate with each other over the backbone bus and/or the circular bus. Each of the communication ports includes backbone bus interface logic, circular bus interface logic, one or more data transfer buffers and/or control logic. The communication ports are preferably able to transfer communications between the backbone bus, the circular bus and/or the modules.

Data transfer network on a computer chip utilizing combined bus and ring

A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing and/or data packing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The data packing logic may optimally fill the bus with data having more or fewer bits than the bus. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Computer system which performs intelligent byte slicing/data packing on

A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Computer system which performs intelligent byte slicing on a multi-byte

A computer chip including multiple on-chip modules connected by an on-chip bus which provides increased performance over current computer chip architectures. The on-chip system bus is a bit sliced bus. Various transmitters/and or receivers are coupled the bit sliced bus. The transmitters and/or receivers include bus interface logic and/or bit transfer logic and/or bit receive logic operatively coupled to the on-chip bit sliced bus which operates to allow different data streams to use different bit lines substantially simultaneously. Thus the bit sliced bus allows different devices to share the bus simultaneously. The bus interface logic and/or the bit transfer logic thus may assign one data stream to a subset of the total bit lines on the bit sliced bus, and fill the unused bit lines with another data stream.

Independent use of bits on an on-chip bus

A system and method for choosing communication pathways for data transfers on a computer chip based on desired latency and bandwidth characteristics. On a computer chip including a network of resources, those resources are allocated based upon the needs of the various components of the computer chip. Typical resources on the computer chip include a first bus with a plurality of data lines and control lines and having first bandwidth and latency characteristics, a second bus with a plurality of data lines and control lines having second bandwidth and latency characteristics, and a plurality of devices coupled to the first bus and second bus. Each device includes interface logic for accessing and performing transfers on the first and second buses. Each device is operable to select either the first or second bus depending on desired bandwidth and latency characteristics. Normally the first bandwidth is greater than the second bandwidth. Each device selects the first bus for higher speed transfers or the second bus for lower speed transfers. When the first latency is shorter than the second latency, each of the devices select the first bus for lower latency transfers and the second bus for higher latency transfers. Other characteristics which may be varies by each device according to the transmission needs of the particular device include clock rate, block size, and bus protocol depending upon desired bandwidth and latency characteristics. For highest possible bandwidth transfers, a multiple bus transfer may be requested by any device.

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Austin, TX, United States of America

J Andrew Lambrecht