University of Westminster

European Space Agency

Izzet Kale

Richard Charles Spicer Morling

Hashem Zare-Hoseini

Andrew Graham Dempster

Piero Angeletti

Ediz Cetin

Adem Coskun

A method of transforming input signals received at N input signal ports to output signals for output at M output signal ports includes generating, from the input signals, first intermediate signals for processing by a fast Fourier transform (FFT), with a predefined number of input ports and output ports corresponding to a size of the FFT; applying the FFT to the first intermediate signals to obtain second intermediate signals; and generating the output signals from the second intermediate signals. The input signal ports are non-uniformly distributed with respect to the input ports in a first signal domain of the input ports; and/or the output signal ports are non-uniformly distributed with respect to the output ports in a second signal domain of the output ports. The disclosure further relates to beamforming networks, reconfigurability in beamforming and beam steering, wideband and narrowband multibeam antenna array devices, FFT processors, programs, and storage media.

Reconfigurable digital beamforming network

In a satellite radio navigation receiver receiving a transmitted radio navigation signal, a method of removing I/Q-mismatches in the received signal, comprising: resolving the received signal into I and Q signal component, and providing them as inputs to a demixing stage which removes unwanted signals, the demixing stage including first and second cross-coupled adaptive filters, whose coefficients are updated by the outputs of the demixing stage, the outputs of the demixing stage representing an IQ mismatch corrected signal. The coefficients are updated only by the polarity values of the outputs, resulting in great simplification. The receiver may be a zero-IF or low-IF receiver, and may operate on time domain or frequency domain signals.

Satellite radio navigation receiver

A method of Digital to Analogue conversion of an input signal Dfor suppressing the effect of clock-jitter in a Delta-Sigma analogue to digital converter, or class D amplifier, comprises charging a capacitor to a reference voltage value (V) during a first phase (&#x3c6;) of a clock signal, discharging the capacitor during a second phase (&#x3c6;) of the clock signal, wherein the discharge is regulated by a biased transistor, responsive to the voltage on the capacitor, in a first part of the second phase to provide an approximately constant discharge current, and regulated in a second part of the second phase for rapidly discharging the capacitor before the end of the second phase; and providing an output (U, OUT) as a function of the discharge current and the input signal D. The output signal U, may be applied as a feedback signal to a loop filter in a Delta-Sigma converter. Alternatively, the output may represent the output of a Class D amplifier.

Digital to analogue conversion

Growing community of inventors

Mitcham, United Kingdom

Izzet Kale