Hitachi, Ltd.

Renesas Electronics Corporation

Izuru Yamada

Toshiro Suzuki

Hiroshi Takatori

Fumiaki Fujii

Osamu Matsubara

Tsutomu Tsuboi

Hiroki Ichikawa

An object of the present invention is to provide means for eliminating a transmission delay when transmitting emergency information for the sake of relief, security, or the like in a wireless device in conformity with the wireless LAN standard in which if radio waves transmitted from peripheral devices are detected, transmission has to be stopped. In a multimode wireless communication scheme having two or more communication schemes, priorities of the communication schemes are set. A high priority or low priority regarding to a message is described in a 'message type' data field of a frame of a controlling channel output from the access point side to the terminal side. When the frame of the controlling channel is decrypted on the terminal side, the message type is confirmed, so that the type of a service channel used thereafter is confirmed and the channel is coupled.

Wireless communication device and communication method of wireless communication device

A pulse generating circuit is provided for generating a pulse having a time width synchronized with an input pulse and corresponding to a reference voltage. The circuit is particularly designed not to be affected by parasitic capacitance. A circuit for charging one electrode of an integrating circuit with a constant current is controlled by turning on or off a switch in response to the input pulse. The other electrode of the integrating capacitor is connected with a reference voltage source by driving a switch in response to a pulse having a pulse width which contains the time period of the input pulse and which is wider than the input pulse. A comparator is provided for comparing the potential at one electrode of the integrating capacitor and ground potential. A desired pulse is generated by a logic circuit which is receives both the output of the comparator and the input pulse.

Pulse width generating circuit synchronized with clock signal and

An integrated circuit is constructed in order that tests can be conducted on a plurality of circuits to determine which of the circuits is defective. In particular, the circuit is constructed to allow such testing with the use of fewer input and output pins for testing. To accomplish this, a first buffer gate circuit, a resistor, and a second buffer gate are connected in series in the order mentioned between the output terminal of a first circuit and the input terminal of a second circuit. An input and output terminal pin for testing is located at a junction point of the resistor and second buffer gate.

Integrated circuit having input and output terminals for testing

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Yokohama, Japan

Izuru Yamada