Kabushiki Kaisha Suwa Seikosha

Kabushiki Kaisha Seikosha

Izuhiko Nishimura

Shinji Morozumi

Masuo Tsuji

Mitsuharu Kodaira

Tadashi Sano

Satoshi Fushimi

An improved semi-conductor integrated circuit wherein the likelihood of permanent breakdown of reverse junctions in the integrated circuitry in response to unexpected high voltages applied thereto is substantially reduced. The semi-conductor integrated circuitry includes at least two field-effect transistors and defines a circuit having at least one output terminal. At least one of the field-effect transistors includes a drain output terminal, and a resistance for reducing the secondary breakdown at the drain output terminal of the reverse junction between the drain output terminal and the semi-conductor integrated circuit substrate, said resistance being disposed intermediate said drain output terminal and said circuit output terminal.

Semi-conductor integrated circuit

An electronic circuit for eliminating chatter from a contact signal is provided. The electronic circuit includes a contact for producing a contact signal representative of a change of state. An asynchronous flip-flop is adapted to receive as a first input the contact signal and as a second input a first periodic pulse signal and in response to the coincidence in the changed state of the contact signal and the first periodic pulse signal producing at least one write-in pulse. A synchronous flip-flop is provided for receiving as a first input the write-in pulses produced by the asynchronous flip-flop and as a second input a second periodic pulse signal, the second periodic pulse signal being synchronized with respect to the first periodic pulse signal so that the leading edge of the first periodic signal defining the coincidence condition precedes a leading edge of the second pulse. The synchronous flip-flop in response to the write-in pulses and the leading edge of the second periodic pulse signal produces an output signal representative of the changed state of the contact signal.

Electronic circuit for eliminating chatter

An electronic timepiece including a variable divider for producing timekeeping signals for the smallest digit of time displayed having a frequency which is not evenly divisible into the frequency produced by the time standard. An oscillator includes a time standard for producing a high frequency time standard signal having a frequency of K.sup.N Hz where K and N are positive integers other than O, and a divider adapted to evenly divide the high frequency time standard signal by K.sup.M, where M is an integer other than O, and in response thereto produce a K.sup.N.sup.-M frequency signal having a frequency not evenly divisible by I.sup.P, where I is a positive integer other than K and P is an integer. A counter is provided for producing output signals representative of a counting cycle in response to an input pulse signal applied thereto, and a display device is coupled to the counter for displaying each count of the cycle thereof. A detecting circuit is coupled to the counter to detect at least one predetermined count of each counting cycle thereof, and in response to each predetermined count produces a detection pulse. The variable divider is coupled to the detection circuit and has a first and second division ratio. The variable divider is adapted to receive the K.sup.N.sup.-M frequency signal and in response thereto divides same by a first division ratio, and in response to each said detection pulse applied thereto divides the K.sup.N.sup.-M frequency pulse by said second division ratio to thereby produce an input pulse signal to the counter having a frequency evenly divisible by I.sup.P.

Electronic timepiece

An electronic digital display timepiece having a locking switch to prevent inadvertent correction of the timepiece, the locking switch being adapted to effect setting of at least one of the digits of time displayed. The electronic timepiece includes a quartz crystal oscillator circuit for producing high frequency time standard signals and a divider circuit including a plurality of divider stages adapted to produce low frequency timekeeping signals in response to said high frequency time standard signals. A display is associated with each of the plurality of divider stages in order to display digits of time in response to the low frequency timekeeping signals counted thereby. The count of certain of the divider stages may be corrected by correction switches provided a locking switch is first displaced from a locking mode to release mode. The locking switch is coupled to at least one divider stage not having a correction switch coupled thereto through circuitry effecting a setting of the divider stage by the operation of said locking switch.

Electronic digital display timepiece correction device

An electronic timepiece having the electronic circuitry formed as a single monolithically integrated circuit chip is provided, a first portion of the circuitry being actuated by a first potential and a second portion of the circuitry being actuated by a second potential higher than said first. The circuit chip includes complementary coupled MOS transistors, the first and second circuit portions operating respectively at first and second logic levels. An interface is provided intermediate said first and second circuit portions, the interface being adapted to effect an interfacing of said logic levels, and an electrical insulation of said first and second circuit portions.

A correction circuit for an electronic timepiece is provided wherein a divider stage can be corrected without effecting correction of any other digit of the electronic timepiece to be corrected. The electronic timepiece includes a quartz crystal oscillator circuit for producing a high frequency time standard signal, a divider circuit including a plurality of divider stages adapted to receive said high frequency timekeeping signals, certain of the divider stages being adapted to produce low frequency timekeeping signals in response to said high frequency timekeeping signals, and display elements associated with said certain divider stages for displaying the time counted thereby in response to said timekeeping signals applied thereto. The electronic timepiece includes a correction circuit including a portion intermediate a divider stage to be corrected and the next divider stage for inhibiting the carry signal from the divider stage to be corrected, whereby the next divider stage is not advanced by the carry signal of the divider stage to be corrected. In one embodiment, an inhibit circuit is corrected to receive the corrected carry signal from divider stage to be corrected and the carry signal from the next-previous divider stage and adapted to inhibit the transmission of that portion of the corrected carry signal representative of a carry due to correction to the next divider stage.

Electronic circuit for individually correcting each digit of time

A timepiece having a quartz crystal vibrator serving as a time standard, a digital display, and integrated divider and C-MOS transistor driving circuits for dividing the high frequency signal from the vibrator into low frequency timing signals for the direct driving of the liquid crystal display. A battery energizes the vibrator and divider circuits but the voltage thereof is insufficient for energizing the display driving circuits. Said voltage is stepped up by a circuit including a rectifier circuit monolithically integrated on the same substrate as said complementary coupled transistor integrated driving circuit and produces a voltage sufficient to energize the driving circuit.

Electric timepiece incorporating rectifier and driving circuits

A chronographic electronic timepiece adapted to display elapsed time wherein the time displayed is rounded off to the nearest half period is provided. Chronographic divider stages adapted to apply signals representative of elapsed time to associated display elements include a binary divider stage adapted to produce elapsed time signal having a period which is the longest time period not displayed by said display elements. A rounding off circuit is provided for advancing the period counted by the binary divider stage in order to advance the count thereof by half a period to effect a rounding off of the time displayed by the display elements.

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Suwa, Japan

Izuhiko Nishimura