Mcnc

Northern Telecom Limited

The University of North Carolina at Chapel Hill

International Business Machines Corporation

Iwona Turlik

Arnold Reisman

Glenn A Rinne

Nicholas G Koopman

Michael R Feldman

Gretchen Maerker Adema

Edward K Yung

Deepak Nayak

Dorota Temple

Giora Dishon

Scott L Jacobs

Neil M Poley

Lih-Tyng Hwang

Robert F Darveaux

A multichip module having high density optical and electrical interconnections between integrated circuit chips includes a substrate overlaying an array of integrated circuit chips. An optical transmitter generates a first optical beam through the substrate and an optical detector receives a second optical beam through the substrate. A hologram is positioned in the path of at least one of the first and second optical beams. An array of electrical contact pads is located on the substrate corresponding to the array of electrical contact pads on the respective integrated circuit chips. A pattern of electrical interconnection lines is located on the substrate for electrically interconnecting the integrated circuit chips. A solder bump between electrical contact pads on the substrate and on the integrated circuit chips establish electrical connections between the substrate and the integrated circuit chips, and also facilitate alignment of the integrated circuit chips with respect to the substrate. The optical transmitter and detector may be mounted on/in the substrate or on/in the integrated circuit chips. The optical transmitter and detector may also be used to provide optical connections external to the microelectronic module, using a holographic substrate to optically link modules. The substrate may also be used to establish optical alignment of the hologram to an underlying optical emitter and/or optical detector without establishing electrical connections thereto.

Microelectronic module having optical and electrical interconnects

A temporary substrate for solder bumps may be used to transfer solder bumps to a microelectronic device. The temporary substrate includes a solder nonwettable surface and a plurality of conductive vias therein. A solder bump is formed on each of the conductive vias and is electrically and mechanically connected thereto. The solder bump extends over the solder nonwettable surface to produce a solder bump cross-sectional area which is greater than the cross-sectional area of the conductive via. A microelectronic device is placed adjacent the temporary substrate with each input/output pad adjacent a respective solder bump. An electrical and mechanical connection is formed between the solder bump and the input/output pad, and the microelectronic device is separated from the temporary substrate with the solder bump remaining connected to the input/output pad. The temporary substrate can also be used for burn-in and testing of microelectronic devices and rework on multichip modules.

Recessed via apparatus for testing, burn-in, and/or programming of

An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips. Solder bumps with different characteristics may be formed by varying the current-time product to each individual pad of the temporary substrate during a plating operation.

Method of forming differing volume solder bumps

Apparatus for testing, burn-in, and/or programming of integrated circuit

A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.

High performance integrated circuit chip package

Method for testing, burn-in, and/or programming of integrated circuit

A multichip module having high density optical and electrical interconnections between integrated circuit chips. An optically transparent substrate is positioned overlying an array of integrated circuit chips mounted on a mounting substrate. The mounting substrate may include a heat sink to remove excess heat from the integrated circuit chips. The multichip module includes integrated circuit chips having optical detectors and optical transmitters to establish optical interconnections therebetween. A hologram is positioned in the optical path between the optical transmitters and the optical detectors. A planar mirror is preferably positioned opposite the hologram to direct the optical beams. The optically transparent substrate also includes an array of electrical contact pads to establish electrical connections with corresponding electrical contact pads on the underlying integrated circuit chips. A pattern of electrical interconnection lines is provided on at least one of the mounting substrate or the transparent substrate to electrically interconnect predetermined ones of the integrated circuit chips.

A method of forming a high density semiconductor structure including one or more buried metal layers. One or more metal layers may be formed on a first semiconductor substrate, with the metal layer or layers being insulated from one another and from the substrate. One or more metal layers may be formed on the surface of a second substrate which may or may not be a semiconductor substrate. The topmost metal layers, either or both of which may have an insulating layer thereon, are placed in contact and heated in an oxidizing ambient atmosphere to form a bond therebetween. One or more vias connect the buried metal layers to the active devices in the substrates. The buried metal layers may form buried power and ground planes and buried metallization patterns for device interconnection.

Method of making high density semiconductor structure

A thermally activated method of depositing a metal on a localized microscopic portion of a substrate, that can be carried out at relatively low process temperatures, and that is particularly useful for depositing metals in an amount and purity sufficient for electrical conductivity on substrates containing microelectronic circuits and devices or their respective precursors. The method comprises heating a substrate in the presence of a vaporized metal-organic composition to a first temperature that is just below the temperature at which the vaporized metal-organic composition will dissociate into a metal and an organic-containing portion, and then raising the temperature of a localized portion of the heated substrate from the first temperature to a second, higher temperature at which the vaporized metal-organic composition will dissociate into a metal and an organic-containing portion but below the temperature at which the organic-containing portion will decompose to produce and deposit organic decomposition products upon the localized portion, and until an amount of the dissociated metal sufficient for electrical conductivity deposits upon the localized portion.

Metal-organic chemical vapor deposition for repairing broken lines in

High density semiconductor structure and method of making the same

A method and resulting structure is disclosed in which a metal-to-metal bond is formed by heating the surfaces to be bonded in an oxidizing ambient atmosphere until the desired bond is achieved. Heating takes place at 700.degree. C.-1200.degree. C. and bonding may be enhanced by applying pressure between the surfaces while heating.

Growing community of inventors

Raleigh, NC, United States of America

Iwona Turlik