Fujitsu Corporation

Fujitsu Semiconductor Limited

Iwao Yamazaki

Takashi Miura

Takahito Hirano

Tsuyoshi Motokurumada

Yuji Shirahige

Takahiro Shikibu

Osamu Moriyama

Masanori Doi

Gen Oshiyama

Akihiro Chiyonobu

Masayuki Kato

Toshio Yoshida

Hiroaki Kimura

Daisuke Mizutani

Aiichiro Inoue

Masateru Koide

Eiji Yamanaka

Shuji Yamamura

Hideo Yamashita

Naohiro Kiyota

Kazuyuki Imamura

Seiji Ueno

Mikio Hondou

Hideki Okawara

Michiharu Hara

Masahiro Doteguchi

Takuma Chiba

Hiroyuki Imai

Goro Yamada

An image processing method performed by a computer, the method including: changing a rendering parameter in a three-dimensional model of a recognition target; and generating teacher data of the recognition target based on the rendering parameter changed by the changing. Thereby, sufficient amount of teacher data can be obtained, without any unfavorable redundancy.

Image processing apparatus, image processing method, and image processing program

A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.

Test circuit and method for controlling test circuit

A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.

Test circuit and method of controlling test circuit

A cache unit comprising a register file that selects an entry indicated by a cache index of n bits (n is a natural number) that is used to search for an instruction cache tag, using multiplexer groups having n stages respectively corresponding to the n bits of the cache index. Among the multiplexer groups having n stages, a multiplexer group in an mstage has 2multiplex circuits. The multiplexer group in the mstage uses a value of an mbit (m is a natural number equal to or less than n) from the least significant bit in the cache index as a control signal. The multiplexer group in the mstage switches all multiplex circuits included in the multiplexer group in the mstage in accordance with the control signal.

Cache unit, arithmetic processing unit, and information processing unit

A processor holds, in a plurality of respective cache lines, part of data held in a main memory unit. The processor also holds, in the plurality of respective cache lines, a tag address used to search for the data held in the cache lines and a flag indicating the validity of the data held in the cache lines. The processor executes a cache line fill instruction on a cache line corresponding to a specified address. Upon execution of the cache line fill instruction, the processor registers predetermined data in the cache line of the cache memory unit which has a tag address corresponding to the specified address and validates a flag in the cache line having the tag address corresponding to the specified address.

Arithmetic processing unit, information processing device, and cache memory control method

A processing apparatus, which contains a processor that executes a program includes a series of instructions, includes a log recording unit configured to record an operation log of the processing apparatus; a managing unit configured to control a recording operation performed by the log recording unit and read the operation log recorded in the log recording unit; an input unit configured to detect, from among the series of instructions of the executed program; a start instruction that starts a process for delivering a control instruction destined for the managing unit to the managing unit and deliver the control instruction to the managing unit in response to the start instruction; and an output unit configured to receive the operation log read by the managing unit.

Processing apparatus and method for acquiring log information

According to an aspect of an embodiment of the invention, an arithmetic processing unit includes a first cache memory unit that holds a part of data stored in a storage device; an address register that holds an address; a flag register that stores flag information; and a decoder that decodes a prefetch instruction for acquiring data stored at the address in the storage device. The arithmetic processing unit further includes an instruction execution unit that executes a cache hit check instruction instead of the prefetch instruction on the basis of a decoded result when the flag information is held, the cache hit check instruction allowing for searching the first cache memory unit with the address to thereby make a first cache hit determination that the first cache memory unit holds the data stored at the address in the storage device.

Arithmetic processing unit and control method for cache hit check instruction execution

A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.

Cache memory having sector function

A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in the FCDR, and merges the stored data with data-to-be-stored in the store data output from the execution unit and stored in the STBs or the WBs to generate new store data. The cache memory controlling unit then writes the generated new store data in the DATA-RAM, generates an ECC from the new store data, and writes the ECC in the ECC-RAM.

Cache controller and cache controlling method

An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.

Error controlling system, processor and error injection method

A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.

Multi-chip module

A pre-fetch control apparatus is equipped with a next-line pre-fetch control apparatus. An address overflowed from a pre-fetch address queueis stored in the next-line pre-fetch control apparatus. An access address issued by a processor unit and stored in a registeris compared with the address stored in the next-line pre-fetch control apparatusand, if the two addresses are identical, a value obtained by adding a data block size &#x3bb; of cache memory to the address stored in the next-line pre-fetch control apparatusis stored again in the next line pre-fetch control apparatus. When the address issued by the processor unit is identical with that stored in the next-line pre-fetch control apparatusa predetermined number of times, the occurrence of continuous accesses is presumed and pre-fetching is carried out for all addresses that have not hit the pre-fetch address queue.

Pre-fetch control apparatus

An information processing apparatus including a main memory and a processor, the processor includes: a cache memory that stores data fetched to the cache memory; an instruction processing unit that accesses a part of the data in the cache memory sub block by sub block; an entry holding unit that holds a plurality of entries including a plurality of block addresses and access history information; and a controller that controls fetching of data from the main memory to the cache memory, while the access by the instruction processing unit to sub blocks of data in a block indicated by another of the entries immediately preceding the one of the entries, in accordance with order of the access from the instruction processing unit to sub blocks in the block indicated by the another of the entries and access history information associated with the one of the entries.

Information processing apparatus and cache memory control method

A correct error correction code can be generated even if a RAM error occurs before writing store data in cache memory (RAM) after confirming that cache line data for storage includes no errors. Before writing the store data, cache line data for storage is stored in a register, the store data is written to the cache memory, the stored contents of the register are merged with the store data, and an error correction code is generated for a result of the merger.

Error correction code generation method and memory control device

In order to increase the operation efficiency of the operation register for holding store data when executing store instructions to store data in a predetermined store area on the main memory or the cache memory, in the present invention, an instruction processing section is adapted so as, when an operation register holding the operation result is determined causes the operation result to be issued from the operation register to store buffers as store data; when the store data are held by the store buffers before the store instruction is held by store ports, a restraint section restrains a reset section from setting a store data hold flag to OFF at a point of time when the store instruction is held by the store ports to maintain the store data hold flag to ON.

Growing community of inventors

Kawasaki, Japan

Iwao Yamazaki