Matsushita Electric Industrial Co., Ltd.

Iwao Hidaka

Tatsuro Juri

Masakazu Nishino

Hiroshi Horikane

Shinya Kadono Kadono

Kiyokazu Hashimoto

Takao Kashiro

Eiji Yamauchi

Yoshiki Yamamoto

Hidemi Oka

The digital processing apparatus includes a high speed response PLL that produces a first clock signal locked on the horizontal synchronization signal included in the video signal input thereto. An analog to digital converter converts the input video signal with respect to the first clock signal into a digitized video signal. A write controller controls a video memory to store the digitized video signal based on the first clock signal. A low speed response PLL produces a second clock signal based on the vertical synchronization signal included in the video signal. A read controller controls the video memory to read out the stored digitized video signal therefrom based on the second control signal. The digital processing apparatus can store and read the digitized video signal to and from the video memory stably, enabling the video signal read from the video memory to be processed effectively and securely.

Digital processing apparatus using two synchronization signals

In an apparatus for executing an algorithm for realizing an orthogonal transform operation such as the 8 points fast cosine transform, by operating on successive sets of data values of a digital signal such as a digital video signal in such applications as high efficiency coding of a digital video signal, a plurality of multiplication operations that are executed during processing of each set of data values are executed sequentially by time division multiplex operation of a single multiplier (32) which is capable of executing a multiplication operation within one sample period of the digital signal, with input and output data values being transferred by selector units (11, 33, 41) between the multiplier and other sections of the apparatus at appropriate times during processing of each set of the input digital signal values. The scale of hardware required for the apparatus is thereby reduced by comparison with an apparatus which employs a plurality of separate multipliers.

Orthogonal transform apparatus for video signal processing

Disclosed is an orthogonal transformation encoder in which after horizontal orthogonal transformation is performed, in parallel to the horizontal and vertical rearrangement of the coefficients for performing vertical orthogonal transformation, detection of interfield coefficient is performed and intra-frame/intrafield modes for the vertical orthogonal transformation are switched. Further, in parallel to the rearrangement of the transformation coefficients for the vertical orthogonal transformation to be in the ascending order from a lower frequency component to a higher frequency component, the amplitude values of the AC components in the block in question are detected to thereby make control on the basis of the amplitude values so that the smaller the amplitude value of the block the smaller the quantizing step width.

Orthogonal transformation encoder

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Higashiosaka, Japan

Iwao Hidaka