Sony/tektronix Corporation

Iwao Akiyama

Ryoichi Sakai

Yasumasa Fujisawa

A DDS type variable frequency signal generator generates a jitter free and stable output signal regardless of the address interval. If the total number of addressable memory locations of a memory storing digital data is divisible without remainder by an initial address interval, then the memory is read every initial address interval with a clock signal of a predetermined frequency. If the total number of addressable memory locations is not divisible without remainder by the initial address interval, then the address interval is modified to a value that is divisible without remainder into the total number of addressable memory locations and the clock frequency is modified in accordance with this modification of the address interval. The memory is read every modified address interval with the modified clock signal.

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Tokyo, Japan

Iwao Akiyama