Semiconductor Components Industries, LLC

Ivo Leonardus Coenen

Dennis Wayne Mitchler

Alexander Heubi

Paulo Jorge Duarte De Jesus

Paulo De Jesus

Clock sources, apparatuses, and methods for operating crystal oscillators. The method includes determining a first time value indicating an amount of time needed to return a trimming value of the crystal oscillator to a predetermined value. The method also includes determining a second time value indicating an amount of time remaining until a clock signal with a predetermined frequency precision is needed. The method further includes detecting that a difference between the first time value and the second time value is greater than or equal to a predetermined step time. The method also includes incrementing a precision reduction value when the difference between the first time value and the second time value is greater than or equal to the predetermined step time. The method further includes adjusting the trimming value of the crystal oscillator based on a difference between the predetermined value and the precision reduction value.

Crystal oscillator power reduction mechanism

Integrated circuits on semiconductor substrates and methods for operating integrated circuits on semiconductor substrates. The method includes adjusting a clock signal, generated by a clock circuit, from a first frequency to a second frequency. The method also includes adjusting a digital supply voltage, generated by a digital supply voltage converter, to a predetermined maximum value for the second frequency. The method further includes adjusting a body biasing voltage, generated by a body voltage converter, to a predetermined value for the second frequency. The method also includes determining, by a controller, speed margins based on logic speed measurements from a logic gate delay line. The method further includes decreasing the digital supply voltage until the speed margins are less than a predetermined threshold margin. The clock circuit, the digital supply voltage converter, the body voltage converter, the controller, and the logic gate delay line are implemented on the semiconductor substrate.

Adaptive voltage scaling with body biasing

According to an aspect, a neural network circuit for decoding weights of a neural network includes a weight memory configured to store encoded weights for the neural network, where the encoded weights includes an index weight word, and a decompression logic circuit configured to retrieve the encoded weights from the weight memory, decode the encoded weights using the index weight word to obtain a sequence of one or more non-pruned weight words and one or more pruned weight words, and provide the sequence of the non-pruned weight words and the pruned weight words to a plurality of input-weight multipliers.

Neural network weight encoding

Hearing instruments, such as hearing aids, may improve a quality of presented audio through the use of a binaural application, such as beamforming. The binaural application may require communication between the hearing instruments so that audio from a left hearing instrument may be combined with audio from a right hearing instrument. The combining at a hearing instrument can require synchronizing audio sampled locally with sampled audio received from wireless communication. This synchronization may cause a noticeable delay of an output of the binaural application if the latency of the wireless communication is not low (e.g., a few samples of delay). Presented herein is a low-latency communication protocol that communicates packets on a sample-by-sample basis and that compensates for delays caused by overhead protocol data transmitted with the audio data.

Low-latency communication protocol for binaural applications

In some aspects, the techniques described herein relate to a system on a chip (SoC) including a first clock divider configured to: receive an oscillator signal at a first frequency; produce, based on the oscillator signal: a first clock signal at the first frequency; and a second clock signal at a second frequency, the second frequency being a division of the first frequency. The first clock divider can selectively provide the first clock signal or the second clock signal as a first output clock signal based on a scaling configuration signal. The first clock divider can produce a frequency indication signal indicating, in combination with the first output clock signal, a start of a new clock period of the second clock signal. The SoC can include a second clock divider configured to provide a second clock output signal based on the first output clock signal and the frequency indication signal.

Apparatus and methods for producing stable clock signals based on a varying frequency source clock

A neural network implementation is disclosed. The implementation allows the computations for the neural network to be performed on either an accelerator or a processor. The accelerator and the processor share a memory and communicate over a bus to perform the computations and to share data. The implementation uses weight compression and pruning, as well as parallel processing, to reduce computing, storage, and power requirements.

Neural network accelerator

Power management for an integrated circuit. At least one example embodiment is a method of operating an integrated circuit on a semiconductor substrate, the method comprising: measuring, by a body voltage controller, a signal indicative of power consumption of devices on the semiconductor substrate, the body voltage controller implemented on the semiconductor substrate; creating, by the body voltage controller, a value indicative of a modified body voltage, the creating based on the signal indicative of power consumption; and modifying, by a body voltage converter on the semiconductor substrate, a body voltage applied to a plurality of transistors on the semiconductor substrate, the modification responsive to the value indicative of the modified body voltage.

Methods and systems of power management for an integrated circuit

Power management for an integrated circuit. One example embodiment is a method of operating a portable audio device including: reading, by a supply controller, a logic speed measurement from a logic gate delay line, the supply controller and the logic gate delay line implemented on a semiconductor substrate; computing, by the supply controller, a speed margin based on the logic speed measurement; creating, by the supply controller, a value indicative of a modified voltage level, the creating based on the speed margin; and modifying, by a main voltage converter on the semiconductor substrate, an output voltage responsive to the value indicative of the modified voltage level.

An electronic system, in some embodiments, comprises: a power source; a load coupled to the power source; an analog-to-digital converter, coupled to the power source and the load, that samples a fluctuating voltage supplied by the power source and generates a digital representation of said fluctuating voltage; control logic, coupled to the analog-to-digital converter, that generates an amplitude correction signal based on said digital representation of the fluctuating voltage and on a target voltage; correction logic, coupled to the control logic, that uses the amplitude correction signal and an audio signal to generate a switch control signal; and an output driver, coupled to the correction logic, that controls coupling between the power source and the load based on the switch control signal.

Active output driver supply compensation for noise reduction

In one embodiment, an audio processing system includes a frequency control block that forms a system clock and a master audio clock. The frequency control block is configured to change a frequency of the system clock and change a relationship between the system clock and the master audio clock so that the frequency of the master audio clock remains substantially constant.

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Coffrane, Switzerland

Ivo Leonardus Coenen