Freescale Semiconductor,inc.

Other

Nxp Usa, Inc.

Ivana Deram

Jean-Michel Francis Reynes

Evgueniy Nikolov Stefanov

Beatrice Bernoux

Rene Escoffier

Jean Michel Reynes

Pierre Jalbaud

Blandino Lopes

Joel Margheritta

Stephane Alves

Frederico Morancho

Adeline Feybesse

A transistor power switch device comprising a semiconductor body presenting opposite first and second faces, an array of vertical field-effect transistor elements for carrying current between the first and second faces is provided. The array of transistor elements comprises at the first face an array of source regions of a first semiconductor type, at least one body region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the second transistor region, and a conductive layer contacting the source regions and insulated from the control electrode by at least one insulating layer.

Power MOS transistor device

A transistor power switch device comprising an array of vertical transistor elements for carrying current between the first and second faces of a semiconductor body and a vertical avalanche diode electrically in parallel with the array of vertical transistors. The array of transistor elements includes at the first face an array of source regions of a first semiconductor type, at least one p region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the p region, and a conductive layer contacting the source regions and insulated from the control electrode. The vertical avalanche diode is configured to conduct breakdown current between the first and second faces in the off state of the device and having a first current carrying diode region of the second semiconductor type in contact with the first face and with the conductive layer and a second semiconductor region of the first semiconductor type electrically connected with the second face.

Power MOS transistor device and switch apparatus comprising the same

A device includes an array of cells, the source regions of the individual cells comprising a plurality of source region branches each extending towards a source region branch of an adjacent cell, the base regions of the individual cells comprising a corresponding plurality of base region branches merging together to form a single base region surrounding the source regions. The junctions between the merged base region and the drain region define rounded current conduction path areas for the on-state of the device between adjacent cells. Floating voltage regions of opposite conductivity type to the drain region are buried in the substrate beneath the merged base region. The features of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths of respective cells. The floating voltage regions include respective islands situated within the current conduction paths.

Power semiconductor device

A method of forming a semiconductor device having an active area and a termination area surrounding the active area comprises providing a semiconductor substrate, providing a semiconductor layer of a first conductivity type over the semiconductor substrate and forming a mask layer over the semiconductor layer. The mask layer outlines at least two portions of a surface of the semiconductor layer: a first outlined portion outlining a floating region in the active area and a second outlined portion outlining a termination region in the termination area. Semiconductor material of a second conductivity type is provided to the first and second outlined portions so as to provide a floating region of the second conductivity type buried in the semiconductor layer in the active area and a first termination region of the second conductivity type buried in the semiconductor layer in the termination area of the semiconductor device.

Method of forming a semiconductor device having an active area and a termination area

A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (). Each individual cell comprises a plurality of radially extending branches () having source regions () within base regions (). The plurality of individual cells are arranged such that at least one branch of each cell extends towards at least one branch of an adjacent cell and wherein the base region () of the extending branches merge together to form a single and substantially uniformly doped base region () surrounding drain islands () at the surface of the semiconductor substrate ().

Power semiconductor device with a base region and method of manufacturing same

The present invention relates to a method of forming a diode ( ) for integration with a semiconductor device comprising the steps of providing a layer ( ) of semiconductor material, forming a dielectric layer ( ) over the layer of semiconductor material, introducing a first conductivity type dopant into the dielectric layer ( ), forming a semi-conductive layer ( ) over the dielectric layer ( ), introducing a second conductivity type dopant into a first region ( ) of the semi-conductive layer and re-distributing the first conductivity type dopant from the dielectric layer ( ) into the semi-conductive layer ( ) so as to form a second region ( ) of the first conductivity type dopant in the semi-conductive layer ( ), the second region ( ) being adjacent the first region ( ) so as to provide a P/N junction of the diode ( ).

Growing community of inventors

Colomiers, France

Ivana Deram