Vlsi Technology, Inc.

Koninklijke Philips Corporation N.v.

Ivan Sanchez

Yu-Pin Han

Ying-Tsong Loh

Landon B Vines

Miguel A Delgado

Danny W Echtle

Koucheng Wu

Walter D Parmantie

An anti-fuse structure and method for forming such structure. In one embodiment, the anti-fuse structure of the present invention includes a dielectric layer which is deposited over a metal layer. The semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. Metal is deposited over the semiconductor substrate and is polished so as to remove the metal which overlies the dielectric layer so as to form a plug which extends through the dielectric layer and which electrically connects to the metal layer. An amorphous silicon block is then deposited, masked and etched so as to form an amorphous silicon block over the plug. A metal layer is then deposited, masked and etched so as to form an interconnect. The amorphous silicon block lies between the metal layer and the interconnect so as to prevent the flow of electrical current until such time as the anti-fuse is activated. The anti-fuse is activated by running a voltage higher than the threshold voltage of the anti-fuse between the interconnect and the plug. Upon activation of the anti-fuse, an electrical connection is made between the interconnect and the metal layer.

Method for forming strapless anti-fuse structure

The invention relates generally to integrated circuits and, in particular, to methods of forming anti-fuse structures during integrated circuit manufacture. In an exemplary embodiment of the invention, a conductive base layer is formed over a semiconductor substrate. An insulating layer is formed on the conductive base layer and is patterned to expose a portion of the conductive base layer. An anti-fuse layer is formed on the insulating layer and the exposed portion of the conductive base layer. A conductive protection layer is formed on the anti-fuse layer. An anti-fuse island is formed by sequentially removing a portion of the conductive protection layer, and underlying portions of the anti-fuse layer and the insulating layer. The conductive base layer is patterned after forming the anti-fuse island. The invention provides a simplified method for the formation of anti-fuse structures which is compatible with submicron device geometries.

Method of forming anti-fuse structure

Metal to amorphous silicon to metal anti-fuse structure

An antifuse structure and method for making the antifuse structure having a doped antifuse layer is disclosed. The doped antifuse layer is preferably deposited over a lower electrode. A barrier layer may then be formed over the doped antifuse layer and an upper electrode may subsequently be deposited over the barrier layer. The method of depositing the doped antifuse layer includes: (a) providing a chemical vapor deposition reactor having a support chuck for supporting a partially fabricated silicon wafer; (b) powering up the chemical vapor deposition reactor and heating the partially fabricated silicon wafer; (c) selecting a dopant species for the antifuse layer (e.g, n-type or p-type); (d) introducing a gaseous mixture of a silane compound and the selected dopant species into the chemical vapor deposition reactor with the aid of a neutral species; and (e) depositing the antifuse layer over the lower electrode. When the antifuse structure is programmed, a wider conduction path is formed in the doped antifuse layer and deprogrammed states are prevented.

Method for making doped antifuse structures

An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.

Antifuse structures

A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.

Methods for fabricating anti-fuse structures

An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.

Methods and apparatus for fabricationg anti-fuse devices

Method of making antifuse structures using implantation of both neutral

Disclosed is a method for programming an antifuse structure. The antifuse structure is programmed by applying an alternating current having alternating current pulses between a bottom and a top electrode to generate a conduction path through an antifuse material sandwiched between the electrodes. The conduction path is formed incrementally due to an electron flow produced as a result of each alternating current pulse thereby defining the conduction path at a substantially centered portion of the antifuse material.

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San Antonio, TX, United States of America

Ivan Sanchez