Microsoft Technology Licensing, LLC

Ivan Nevraev

Jason Matthew Gould

Martin J I Fuller

Mark Stefan Grossman

Cole Brooking

J Andrew Goossen

Xiang Li

Eric Christoffersen

David McCarthy Peixotto

Marcelo Lopez Ruiz

James D Stanard

Jason Strayer

Matthew L Bronder

Vishal Chandra Sharma

Martin Jon Irwin Fuller

James Andrew Goossen

Adam James Miles

Brian Bo Rasmussen

Matthew Lawrence Bronder

Adam J Miles

To optimize the compilation of shaders for execution within an application, a computer system discovers the context in which the shaders are executed. The application is compiled and executed on a target platform. Snapshots of the application during execution are captured. A snapshot includes data and commands passed between the central processing unit and the graphics processing unit of the target platform to generate a single frame of graphics data. The shaders used in these snapshots are identified. These shaders are compiled with a number of different permutations of available compiler options, resulting in sets of differently compiled shaders. The snapshot is re-executed with the sets of differently compiled shaders, and performance is measured. The set of compiler options that results in compiled shaders providing better performance can be used as the set of compilation parameters for the set of shaders for this application.

Optimizing compilation of shaders

Examples described herein generally relate to systems and method for streaming a video game at a client device. The client device may transmit video game controls to a streaming server. The client device may receive a video stream encoding video images generated in response to the video game controls from the streaming server. The client device may determine that a video image of the video stream to display in a frame has not been completely received at a designated time prior to display of the frame. The client device may determine an image transformation based on a history of the video images and motion vectors for the video stream. The client device may apply the image transformation to a portion of one or more images corresponding to previous frames. The client device may display a substitute video image in the frame including the portion of the transformed image.

Dead reckoning and latency improvement in 3D game streaming scenario

Methods and devices for lowering precision of computations used in shader programs may include receiving program code for a shader program to use with a graphics processing unit (GPU) that supports half precision storage and arithmetic in shader programs. The methods and devices may include performing at least one pass on the program code to select a set of operations within the program code to lower a precision of a plurality of computations used by the set of operations and evaluating a risk of precision loss for lowering the precision to a half precision for each computation of the plurality of computations. The methods and devices may include generating edited program code by rewriting the computation to the half precision in response to the risk of precision loss being a precision loss threshold.

Acceleration of shader programs by compiler precision selection

Methods and devices for managing first-in first-out (FIFO) queues in graphics processing are described. A dispatcher thread can receive a value of a write done pointer indicating a next memory location following one or more memory locations to which data has been written by a write thread of a graphics processing unit (GPU). The dispatcher thread can accordingly launch, based at least in part on the value of the write done pointer, multiple read threads on the GPU to read, in parallel and based on the write done pointer, the data from the FIFO queue.

FIFO queue, memory resource, and task management for graphics processing

Methods and devices for index buffer block compression in a computer system include a compressor in communication with a graphical processing unit (GPU). The methods and devices include selecting one or more primitives of at least a portion of a mesh formed by a total number of primitives for inclusion within a compressed index buffer block, the one or more primitives each associated with a number of indices each corresponding to a vertex within the mesh. The methods and devices may identify at least one redundant index in the number of indices associated with the one or more primitives of the compressed index buffer block. The methods and devices removing the at least one redundant index from the number of indices associated with the one or more primitives of the compressed index buffer block to form the compressed index buffer block as a set of one or more unique indices.

Index buffer block compression

Enhanced data buffer control in data systems is presented herein. In one example, a method includes establishing a pool of available memory pages tracked by memory pointers for use in a data structure, and processing requests for storing data to identify ones of the requests indicating data sizes that exceed a capacity of current pages included in the data structure. The method includes providing first pointers indicating start locations in the data structure to begin writing associated data, count information indicating quantities of the associated data able to be written in the current pages, and second pointers indicating at least one additional page in the data structure into which the associated data can be spanned from the current pages, where the at least one additional page is allocated from the pool of available memory pages in accordance with a fullness threshold for the data structure.

Flexible sizing for data buffers

Methods and devices for rendering graphics in a computer system include a graphical processing unit (GPU) with a flexible, dynamic, application-directed mechanism for varying the rate at which fragment shading is performed for rendering an image to a display. In particular, the described aspects include determining, at a rasterization stage, map coordinates based on coarse scan converting a primitive of an object, the map coordinates indicating a location on a sampling rate parameter (SRP) map of a fragment within the primitive of the object, and identifying a lookup value for the fragment within the primitive of the object based at least on map coordinates, and calculating a respective fragment variable SRP value for the fragment within the primitive of the object based at least on the lookup value.

Variable rate shading

Methods and devices for generating program code representations may include receiving program code or edited program code for an application executing on the computer device. The methods and devices may include receiving an identification of a selected pipeline from a plurality of pipelines that defines a plurality of passes of actions to execute on the program code or the edited program code to optimize the program code or the edited program code. The methods and devices may include running the selected pipeline and generate optimizer output with a program code representation of the program code.

Interactive code optimizer

Methods and devices for managing first-in first-out (FIFO) queues in graphics processing are described. A write operation can be executed by multiple write threads on a graphics processing unit (GPU) to write data to memory locations in the multiple pages of memory. The write operation can also include allocating additional pages of memory for the FIFO queue where a write allocation pointer is determined to achieve a threshold, such to grow the FIFO queue before the memory is actually needed for writing. Similarly, comprises a read operation can be executed by multiple read threads to read data from the memory locations. The read operation can also include deallocating pages of memory back to a memory pool where a read done pointer is determined to achieve a threshold, such as an end of a page.

Various approaches to performing non-divergent parallel traversal operations for a bounding volume hierarchy ('BVH') during ray tracing are presented. For example, a computer system has a processing unit with threads that, collectively, perform ray tracing for a group of rays in parallel in a computer-represented environment, which includes geometric objects (such as triangles) enclosed in the BVH. Each of the threads receives parameters for a given ray and traverses the BVH to determine an intersection, if any, between the given ray and one of the geometric objects. The order of traversal of the BVH is synchronized between threads for the rays of the group, for example, using a cross-group operation such as a ballot operation. In this way, the overall speed of the BVH traversal can be improved in many cases, while avoiding code divergence and data divergence in extra-wide single-instruction, multiple data ('SIMD') graphics processing unit (&#x201c;GPU&#x201d;) architectures.

Non-divergent parallel traversal of a bounding volume hierarchy

Methods and devices for rendering graphics in a computer device include receiving, at a graphics processing unit (GPU), a memory location address of a portion of a primitive to be rendered along with an indication of one or more values of one or more pixel shader parameters for the portion of the primitive, selecting, by the GPU, a pixel shader from a plurality of possible pixel shaders based on the indication of the one or more values of the one or more pixel shader parameters, and generating, by the GPU, at least one output of a render target of the portion of the primitive based on applying the pixel shader to the portion of the primitive.

Multiple shader processes in graphics processing

Among the various embodiments disclosed herein are example methods for using real-time raytracing in a hybrid approach along with screen space reflections. In certain implementations, the two approaches are combined in a process that decides whether to use screen space reflections or raytracing for a given pixel during a preliminary analysis (pre-pass) of the pixel to be rendered.

Hybrid raytracing approach for modeling light reflection

Enhanced data buffer control in data systems is presented herein. In one example, a method of handling data buffer resources in a graphics processor includes establishing a pool of available memory pages tracked by memory pointers for use in a growable data structure. Responsive to requests by at least a shader unit of the graphics processor for space in the growable data structure in which to write shader data, the method includes providing to the shader unit at least write pointers to locations within memory pages from the growable data structure in accordance with data sizes indicated in the requests. Responsive to exceeding a threshold fullness of the growable data structure, the method includes allocating at least one further memory page from the pool of available memory pages for inclusion in the growable data structure.

Growing community of inventors

Redmond, WA, United States of America

Ivan Nevraev