Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Ivan Miro Panades

Robert Polster

Yvain Thonnart

José-Luis Gonzalez Jimenez

Eric Guthmuller

The invention concerns a frequency locked loop comprising: a digitally controlled oscillator () configured to generate a frequency signal (F); a frequency counter () configured to generate an estimate (f_EST) of the frequency of the frequency signal based on a reference clock signal (CLK_REF); and a controller () configured to generate a digital control signal (C_FREQ) for controlling the digitally controlled oscillator based on the estimated frequency, wherein the controller is clocked by a further clock signal (CLK) having a variable frequency, and the controller is configured to generate a trigger signal (AUTO_CLEAR) for triggering a counting phase of the frequency counter.

Frequency locked loop with fast reaction time

A receiving circuit of a communications link comprises: a first data buffer configured to input, under control of a first clock signal, data of a first data stream transmitted by a transmitting circuit, and to generate a credit trigger signal indicating when a data value is read from the first data buffer, wherein data is read from the first data buffer, or from a further data buffer coupled to the output of the first data buffer, under control of a second clock signal; and a credit generation circuit configured to generate, based on the credit trigger signal, a credit signal for transmission to the transmitting circuit under control of the first clock signal, the credit signal indicating that one or more further data values of the first data stream can be transmitted by the transmitting circuit.

Circuit and method for credit-based flow control

The invention concerns a circuit comprising: a voltage generator adapted to generate a variable supply voltage for powering a processing core; a frequency generator adapted to generate a variable frequency clock signal of the processing core and comprising a frequency locked loop having: a digitally controlled oscillator configured to generate the variable frequency clock signal; and a controller () configured to generate a digital control signal (C_FREQ), wherein the controller is configured to implement a frequency transition of the variable frequency clock signal from a first frequency to a second lower frequency by generating: a first value of the digital control signal (C_FREQ) to apply a first reduction in the frequency of the variable frequency clock signal to a third frequency lower than the second frequency; and further values of the digital control signal (C_FREQ).

Frequency locked loop with fast voltage/frequency transition

A method of circuit conception including performing static timing analysis on a circuit design to identify a first subset of the synchronous devices having at least one input path with a slack time below a first threshold; simulating the circuit design using one or more functional test patterns to identify a second subset of the synchronous devices for which the number of activations during the simulation is above a second threshold; selecting at least one synchronous device forming part of both of the first and second subsets; and modifying the circuit design to include, for each selected synchronous device, a detection circuit coupled to one or more inputs of the selected synchronous device.

Method for equipping registers of an integrated circuit to detect timing violations

An optical receiver adapted to convert a received optical signal into a phase change of a timing signal to generate a first modified timing signal and to generate a data signal by comparing the first modified timing signal with a reference signal.

Optical data receiver with relative phase detector

A clock receiver including: a ring oscillator adapted to generate a clock signal, the ring oscillator having a sequence of N inverters, an input of a first inverter being coupled to a feedback node, an input of a second inverter being connected to an output of the first inverter and to an input line for receiving a reference clock signal, and an output of the second inverter or of a third inverter providing a first phase signal; a further sequence of inverters, an input of a first further inverter being coupled to the feedback node, and an output of another further inverter providing a second phase signal; and a control circuit for adjusting an oscillation frequency of the ring oscillator based on the relative phases of the first and second phase signals.

Injection locked clock receiver

A data reception device comprises: a first data input for receiving a first data signal and a clock input for receiving a clock signal; and a stability detection circuit adapted to generate: a first error signal indicating when a data transition of the first data signal occurs during a first period at least partially before a first significant clock edge of the clock signal; and a second error signal indicating when a data transition of the first data signal occurs during a second period at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal for adjusting the sampling time of the first data signal based on said first and second error signals.

Method and device for improving synchronization in a communications link

A method is presented for characterizing a digital circuit for determining an optimum operating point of the digital circuit. The digital circuit includes sequential elements; conducting data paths; a clock tree; a time fault sensor receiving as input a data signal and configured to detect during a detection window a transition of the data signal; and a system for setting first and second operating parameters of the circuit. The method includes a) activating a conducting data path leading to the sequential element coupled to the sensor; b) determining, for a given value of the first parameter, a first value of the second parameter from which the sensor detects a transition of the data signal during the detection window, the values of the first and second parameters defining an operating point of the circuit; and c) correcting the operating point.

Method for characterizing the operation of a digital electronic circuit and digital electronic circuit

A system for managing correspondence between a cache memory, subdivided into a plurality of cache areas, and a main memory, subdivided into a plurality of memory areas, includes: a mechanism allocating, to each area of the main memory, at least one area of the cache memory; a mechanism temporarily assigning, to any data row stored in one of the areas of the main memory, a cache row included only in one cache area allocated to the main memory area wherein the data row is stored; and a mechanism generating and updating settings of the allocation by activating the allocation mechanism, the temporary assigning mechanism configured to determine a cache row to be assigned to a data row based on the allocation settings.

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Grenoble, France

Ivan Miro Panades