Intel Corporation

Ivan Herrera Mejia

Kenneth D Shoemaker

Ryan Donovan Wells

Zeev Offen

Altug Koker

Sanjib Sarkar

Vishram Sarurkar

Yun He

Vijay K Vuppaladadium

Ruchira K Liyanage

Pavel Konev

Shrinivas Venkatraman

Narender R Nagulapally

Manuel A Aguilar Arreola

Rakesh Mehta

Sahar Sharabi

Ehud Cohn

Raghav Ramesh Lakshmi

Mohsin Ali

Eyal Pniel

Abraham Halevi Fraenkel

Gowtham Raj Karnam

Fylur Rahman Sathakathulla

Renu Patle

Hagay Spector

Hanmanthrao Patli

Joshua D Louie

Maulik Joshi

Andrea R Vavra

Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.

Hardware software communication channel to support direct programming interface methods on FPGA-based prototype platforms

Embodiments including systems, methods, and apparatuses associated providing an interface between a north complex and a south complex of a system on a chip (SoC). In embodiments, the north complex may include a microcontroller in an input signal requirement. A power-on control block may be coupled with the microcontroller, and the power-on control block may be configured to receive a control signal from a component of the south complex, and alter the control signal based at least in part on the input signal requirement of the microcontroller.

Interface for communication between circuit blocks of an integrated circuit, and associated apparatuses, systems, and methods

An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen.

Indicating critical battery status in mobile devices

Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some embodiments, performance of a link is evaluated at a plurality of equalization values and one of the plurality of equalization values is selected for the link based on comparison of a plurality of margin values that are to be determined for each of the plurality of equalization values. Other embodiments are also claimed and/or disclosed.

Preset evaluation to improve input/output performance in high-speed serial interconnects

Methods and apparatus related to adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications are described. In some embodiments, a first bit pattern is detected, at a first agent, that indicates a speculative entry by a second agent into a low power consumption state and one or more control loops are frozen. A second bit pattern is detected (after entering the low power consumption state) that indicates exit from the low power consumption state by the second agent and the one or more control loops are unfrozen (e.g., in a specific order). Other embodiments are also claimed and/or disclosed.

Adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applications

Technologies for implementing a secure boot using multiple firmware sources are described. One or more fuses of a processing device can be configured. Based on such configuration, one or more keys can be generated. Based on the configuration of the various fuses, an operation of a firmware device can be initiated. Using the generated key(s), a protected section of the firmware device can be accessed.

Method and apparatus for implementing a secure boot using multiple firmware sources

A system, semiconductor device and method for providing a controlled system reset sequence with lower power consumption without dependency on fuses, PLL's and external XTAL's. A method to simplify a boot sequence by using a ring oscillator that compensates for voltage and temperature variations while also removing the dependency on parallel fuses, PLL's and external XTAL's.

Method and apparatus for controlled reset sequences without parallel fuses and PLL'S

In general, in one aspect, the disclosure describes creation of a randomization list that includes only a subset of the logic states of an integrated circuit (IC). The subset being selectable by signal so as to define logic states that can be randomized for specific events. The randomization list is during simulation to randomize the logic states defined therein to simulate a specific event occurring during operation of the IC. For example, the randomization list may include those signals that can be randomized upon exiting from a powered down state (e.g., deep power down, C6). The signals that can be randomized may be defined by excluding the signals that cannot be randomized (those still receiving power in the C6 mode). The contents of registers of the IC can be confirmed after the randomization and exit from the C6 mode.

Simulating loss of logic power state due to processor power conservation state

Growing community of inventors

Folsom, CA, United States of America

Ivan Herrera Mejia