Freescale Semiconductor,inc.

Nxp Usa, Inc.

Ivan Carlos Ribeiro Nascimento

Pedro Barbosa Zanetta

Andre Luis Vilas Boas

Sunny Gupta

Adriano Marques Pereira

Carl Culshaw

Garima Sharda

Akshay Kumar Pathak

Walter Luis Tercariol

Fernando Zampronho Neto

Edevaldo Pereira Silva, Jr

Akshat Gupta

Walter Luis L Tercariol

Richard T L Saez

Systems and methods for managing cold-crank events. In an embodiment, a method may include detecting a cold-crank event and setting a switching circuit to a non-conductive state, where the switching circuit is configured to couple a first regulator to a memory circuit such that setting the switching circuit to the non-conductive state de-couples the memory circuit from the first regulator. The method may also include setting the switching circuit to a conductive state in current limitation mode during a recovery period following the cold-crank event to re-couple the memory circuit to the first regulator. In another embodiment, an electronic device include a switching circuit, a first regulator coupled to a first terminal of the switching circuit, a second regulator coupled to a second terminal of the switching circuit, a logic circuit coupled to the switching circuit, and a memory circuit coupled to the second terminal of the switching circuit.

Cold-crank event management

In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.

Power gating techniques with smooth transition

Systems and methods for transition control in a hybrid Switched-Mode Power Supply (SMPS). In some embodiments, a hybrid SMPS may include linear circuitry configured to produce an output voltage proportional to a variable duty cycle when the SMPS operates in linear mode and hysteretic circuitry coupled to the linear circuitry, the hysteretic circuitry configured to cause the duty cycle to assume one of two predetermined values when the SMPS operates in hysteretic mode. The hybrid SMPS may also include transition circuitry coupled to the linear circuitry and to the hysteretic circuitry, the transition circuitry configured to bypass at least a portion of the linear circuitry in response to the hybrid SMPS transitioning from the hysteretic mode to the linear mode.

Transition control for a hybrid switched-mode power supply (SMPS)

An integrated circuit includes a delay compensation circuit () that further includes a terminal for receiving a varying signal from a circuit external to the integrated circuit; a sampler circuit that samples and holds a present value of the varying signal at each occurrence of a transition in a digital signal; an integrator, coupled to the sampler circuit, that integrates a voltage difference between a sample of the varying signal and a reference signal, and that outputs results of the integration, wherein a time constant of the integrator is greater than a period of the varying signal; a waveform generator that generates a decreasing voltage in response to a transition in a second digital signal; and a comparator that has one input terminal for receiving the decreasing voltage, an inverted input terminal for receiving the results, and an output terminal for outputting a signal that generates an output signal.

Delay compensation circuit

Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and where the voltage has a value outside of a voltage supply range of the logic circuit. In another embodiment, a semiconductor device may include a biasing circuit configured to generate a voltage that varies according to a temperature of the semiconductor device and a power switch operably coupled to the biasing circuit, where the voltage is applied to a gate terminal of the power switch, and where the voltage has a value outside of a voltage supply range of the power switch.

Temperature dependent biasing for leakage power reduction

Power switches with current limitation and zero Direct Current (DC) power consumption. In an embodiment, an integrated circuit includes switching circuitry coupled between a voltage supply node and a given one of a plurality of power domains, the switching circuitry configured to limit an amount of current drawn by the given power domain from the voltage supply node during a transition period, the switching circuitry further configured to consume zero DC power outside of the transition period. In another embodiment, a method includes controlling, via a switching circuit coupled between a voltage supply and an integrated circuit, an amount of current drawn by the integrated circuit from the voltage supply during a transition period; and causing the switching circuit to consume no static power during periods of time other than the transition period.

Power switch with current limitation and zero direct current (DC) power consumption

Startup circuits with native transistors. In some embodiments, a startup circuit may include a first inverter configured to receive a bandgap voltage (V) from a bandgap reference circuit and to produce an output voltage (V), and a second inverter operably coupled to the first inverter to form a latch, the latch configured to maintain a value of V, the second inverter including a native transistor, the native transistor having a gate terminal coupled to Vand a source terminal coupled to V. In other embodiments, a method may include receiving Vat a startup circuit and outputting Vconfigured to change in response to Vrising above Vor falling below V, where the power consumption of the startup circuit is based at least in part upon a voltage value applied to a source terminal of a native transistor within the startup circuit.

Startup circuits with native transistors

A device () includes a circuit () and a driver stage () therefor. The circuit includes two sub-circuits (and). The driver stage includes switcher logic () that produces signals that control switching on and off of the sub-circuits. The switcher logic also produces other signals in advance of the signals that control the switching of the sub-circuits. The driver stage includes delay compensations circuits (and), coupled to the switcher logic and to the circuit, that produce timing signals for the switcher logic. The timing signals are closely aligned with moments that a changing voltage at a node between the sub-circuits passes through threshold voltages. The timing signals compensate for all delays of signals through the device such that a period that both sub-circuits are off is minimized, while ensuring that both sub-circuits are not on at a same time.

A testing circuit in an integrated circuit indirectly measures a voltage at a node of other circuitry in the integrated circuit. The testing circuit includes a transistor having a control electrode, a first conducting electrode coupled to a first pad, a second conducting electrode coupled to a terminal of a power supply, and one or more switches for selectively coupling the control electrode to one of the node and a second pad. A method includes determining a relationship between drain current and gate voltage of the transistor when the control electrode is coupled to the second pad. A voltage at the node is determined by relating the current through the first conducting electrode of the transistor when control electrode is coupled to the node.

Circuit and method for measuring voltage

Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.

Power monitoring circuitry

A touch sensing interface () includes a noise touch sensing circuit () that utilizes electromagnetic (EM) noise in a touch panel () to determine whether a pad of the touch panel is touched, such as by a finger of a user. The noise touch sensing circuit detects noise in a first pad () and in a second pad () of the touch panel, compares power of the noise in the first pad to power of noise in the second pad, and outputs a signal () indicative of the first pad being touched when power of noise in the first pad exceeds power of noise in the second pad by a pre-selected amount. The touch sensing interface may include a capacitive touch sensing circuit () and a controller () that selectively actuates the noise touch sensing circuit and the capacitive touch sensing circuit.

Touch sense interface circuit

A voltage reference module of an integrated circuit device includes a current source to apply a current to a set of voltage cells, thereby generating a voltage drop across each cell. The voltage cells are configured such that the individual voltage drop associated with each cell in response to the application of the current is relatively stable over a temperature range. The voltage reference module generates a voltage based on the voltage drops across the voltage cells, and therefore the generated voltage is also stable over the temperature range. Bypass switches can be connected across each voltage cell whereby the switches can be individually opened and closed to include or exclude cells in generation of the reference voltage. In an embodiment, the switches are set during a trimming process for the integrated circuit device so that the voltage reference module provides a specified voltage.

Voltage reference device and methods thereof

A transceiver suitable for interfacing a logic device to a shared bus includes a transmit node that receives an input signal from the logic device and an I/O node, that is coupled to the shared bus. The transceiver may be designed for use with a shared-bus, single master, multiple slave architecture, e.g., a Local Interconnect Network (LIN). In a LIN compliant implementation, the transceiver may be suitable for use in at least some types of automobiles and other motorized vehicles. Control logic coupled to the transmit node may assert a current driver enable signal in response to detecting an assertion of the input signal. A current driver of the transceiver is configured to draw a time varying driver current from the shared bus node after detecting an assertion of the current driver enable signal. The driver current may cause a sinusoidal transition of the shared bus voltage.

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Campinas, Brazil

Ivan Carlos Ribeiro Nascimento