Synopsys, Inc.

Ivailo Nedelchev

James David Sproch

Janet L Olson

Ashutosh S Mauskar

Yueqin Danny Lin

Yuegin Danny Lin

A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell &ldquo;library&rdquo; within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition. Specifically, library designers are allowed to specify multiple internal power tables for each output with different &ldquo;related_pins&rdquo; fields. To take advantage of the path dependent power modeling, library designers can specify multiple power tables in the library cell with different sets of related_pins. Path dependent power modeling is important for those cells for which the path of the toggle makes the cell consume more or less power than the otherwise recorded &ldquo;average&rdquo; power rating used in conventional libraries. One example is the set/reset (SR) flip-flop.

Path dependent power modeling

A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q&prime; outputs. A library developer can specify a 3-D power table having three indices, input transition time, output1 capacitance (e.g., for Q), and output2 capacitance (e.g., for Q&prime;). The power value output is then an accurate measure of the total power consumed by the dual output cell during the output transition.

Three-dimensional power modeling table having dual output capacitance indices

A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell 'library' within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition. Specifically, library designers are allowed to specify multiple internal power tables for each output with different 'related.sub.-- pins' fields. To take advantage of the path dependent power modeling, library designers can specify multiple power tables in the library cell with different sets of related.sub.-- pins. Path dependent power modeling is important for those cells for which the path of the toggle makes the cell consume more or less power than the otherwise recorded 'average' power rating used in conventional libraries. One example is the set/reset (SR) flip-flop.

A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q' outputs. A library developer can specify a 3-D power table having three indices, input transition time, output1 capacitance (e.g., for Q), and output2 capacitance (e.g., for Q'). The power value output is then an accurate measure of the total power consumed by the dual output cell during the output transition.

Three-dimensional power modeling table having dual output capacitance

A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular pin (e.g., input, output, bidirectional, internal) based on a prescribed condition of the state of signals that exist contemporaneously with a signal transition on the particular pin. This is referred to as state dependent power modeling. A different power consumption value can be provided for each different modeled state. The logic cells and the power consumption model for them are stored in a logic cell 'library' within the computer system. State dependent power modeling of the present invention allows library designers to specify a different set of power values depending on the condition of one or more pins of the library cell (e.g., the library's representation of the logic cell). Specifically, library designers are allowed to specify a 'when' condition with their power tables. To take advantage of the state dependent power modeling, library designers can specify multiple power tables in the library cell with different when conditions. State dependent power modeling is important for those cells for which a certain condition of the pins makes the logic cell consume more or less power than the otherwise recorded 'average' power rating used in conventional libraries. Examples of these cells are random access memories (RAMs), input/output cells (IOs), and enabled flip-flops.

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Santa Clara, CA, United States of America

Ivailo Nedelchev