Cypress Semiconductor Corporation

Longitude Flash Memory Solutions Ltd.

Linear Technology Corporation

Longitude Elash Memory Solutions Ltd

Iulian Constantin Gradinariu

Vijay Raghavan

Keith A Ford

John J Silver

Sean B Mulholland

Gary Peter Moscaluk

Roger J Bettman

Cristinel Zonte

Samuel Leshner

Vineet Argrawal

Bogdan I Georgescu

Vijay Kumar Srinivasa Raghavan

Danny L Rose

Jayant Ashokkumar

Bogdan Samson

James D Allan

Edson Wayne Porter

Nandakishore Raimar

Mohandas Sivadasan

Abhisek Dey

Brajveer Singh

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Low standby power with fast turn on method for non-volatile memory devices

One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, an oscillator comprises a voltage controlled oscillator configured to generate an output clock based on a drive signal, a frequency to voltage converter having a time constant and configured to generate a feedback voltage having a decay cycle based on the time constant and a frequency based on a frequency of the output clock, and an integrator configured to generate the drive signal based on an integration of the feedback voltage and a reference voltage.

Closed loop oscillator

A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.

Systems, methods, and devices for providing power to low energy circuits include inrush circuits. Devices include a regulator that includes at least one driver device configured to generate a first current associated with a load comprising a low energy integrated circuit. Devices also include a bias generator configured to generate a second current to charge a load capacitor coupled with a power terminal of the low energy integrated circuit. Devices further include an enable circuit configured to enable the bias generator and disable the regulator responsive to a load voltage being below a threshold voltage, and further configured to enable the regulator to generate the first current and disable the bias generator responsive to the load voltage being above the threshold voltage.

Low inrush circuit for power up and deep power down exit

Low standby power with fast turn on for non-volatile memory devices

A circuit includes a biasing circuit that includes a diode stack coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a transistor, a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the diode stack in response to a transition of the ISO signal between a first voltage and a second voltage. The biasing circuit also is configured to output a signal to a level shifter to hold an output of the level shifter in a known state for a specified amount of time after power-up of the circuit for proper operation of the level shifter.

Biasing circuit for level shifter with isolation

A capacitance sensing device can include a reference circuit configured to connect to a reference capacitance, and to generate an electrical reference signal that varies over time according to the reference capacitance and a compare signal; a sense circuit configured to connect to a sense capacitance, and to generate an electrical sense signal that varies over time according to a sense capacitance; a compare circuit having compare inputs coupled to receive the sense signal and the reference signal, and a compare output that provides the compare signal; and a value generation circuit configured to generate an output value corresponding to the compare signal over a predetermined time period.

Differential sigma-delta capacitance sensing devices and methods

A circuit includes a biasing circuit that includes a load circuit coupled to a first node. The biasing circuit can output a biasing signal on the first node. The biasing circuit also includes a timer component and a current source. An input of the timer component is coupled to receive an isolation signal. The current source is configured to inject current for a period of time into the load circuit in response to a transition of the ISO signal between a high voltage and a low voltage. The biasing circuit also includes circuitry to generate an isolation delayed (ISO_DEL) signal. The ISO_DEL signal has a high voltage in response to the biasing signal being within a first threshold level and the ISO_DEL signal has a low voltage in response to the biasing signal being within a second threshold level. The biasing circuit outputs the ISO_DEL signal.

A monolithic voltage reference circuit may include a voltage-mode band-gap reference circuit, a temperature independent differential current source, and a temperature dependent differential current source. The voltage-mode band-gap reference circuit may include an error amplifier having differential input nodes. The temperature independent differential current source may be configured to add in or subtract from the differential input nodes a substantially temperature independent differential current with an allocation between the nodes that is controlled by a selectable output voltage trim setting. The temperature dependent differential current source may be configured to add in or subtract from the differential input nodes a substantially temperature dependent differential current with an allocation between the nodes that is controlled by a selectable temperature drift trim setting.

Voltage-mode band-gap reference circuit with temperature drift and output voltage trims

Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.

Substrate bias feedback scheme to reduce chip leakage power

A method of biasing a circuit includes generating a control bias signal based on a difference between a leakage current of a baseline circuit and a reference signal; applying the control bias signal to a charge pump circuit to set a value of a reverse body bias voltage output from the charge pump, the control bias signal providing analog control of a digital clock of the charge pump circuit; and applying the reverse body bias voltage to a body of the baseline circuit.

A substrate bias circuit may measure a leakage current of a baseline device, compare the leakage current with a reference current, and based on the comparison, adjust a reverse body bias voltage applied to a body of the baseline device.

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Colorado Springs, CO, United States of America

Iulian Constantin Gradinariu