Synopsys, Inc.

Synplicity, Inc.

Other

Iota Technology, Inc.

Iu-Meng Tom Ho

A depletion-mode FeFET ('FeDFET') is programmable to a first programmed state, under a first set of voltage biasing conditions, and to a second programmed state, under a second set of voltage biasing conditions. In both the first and second programmed states, the storage transistor has a threshold voltage that is not greater than 0 volts. A memory circuit may be organized as memory cells, with each memory cell including select transistors, transistor switches and FeDFETs in a static random-access memory (SRAM) cell configuration.

Depletion mode ferroelectric transistors

A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid. A similar embodiment represents grid routing technique where the signals are routed between layers N and N+1. Another embodiment enables signals to be shielded by opposite power and ground grids on left, right, top and bottom. Additional embodiments also include utilization of similar mesh utilized in standard cell and/or in the gate array routing area or any other area where any other signal line is to be shielded.

Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device

An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used to store two true and complementary data bits, are used to store two, three, or four data bits depending on the noise margin allowed and bit width selection. The memory can be ferroelectric memory FeRAM, a flash memory, a ROM, a dynamic memory DRAM, an OUM, a MRAM, a NAND memory, or a NOR memory.

Electronic memory with binary storage elements

A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid. A similar embodiment represents grid routing technique where the signals are routed between layers N and N&plus;1. Another embodiment enables signals to be shielded by opposite power and ground grids on left, right, top and bottom. Additional embodiments also include utilization of similar mesh utilized in standard cell and/or in the gate array routing area or any other area where any other signal line is to be shielded.

Growing community of inventors

Milpitas, CA, United States of America

Iu-Meng Tom Ho