Intel Corporation

Ittai Anati

Carlos V Rozas

Francis X Mckeen

Vedvyas Shanbhogue

Ilya Alexandrovich

Vincent R Scarlata

Simon P Johnson

Gilbert A Neiger

Rebekah M Leslie-Hurd

Uday R Savagaonkar

Michael A Goldsmith

Krystof C Zmudzinski

Wesley Hamilton Smith

Zeev Sperber

Somnath Chakrabarti

Alex Berenzon

Barry E Huntley

Raghunandan Makaram

Shay Gueron

Chris J Newburn

Bryant E Bigbee

Mona Vij

Jacob Doweck

Amy L Santoni

Siddhartha Chhabra

Amit Gradstein

Dion Rodgers

Vinodh Gopal

Wajdi K Feghali

Hong Wang

Simon Rubanovich

Sean M Gulley

Xiang Chris Zou

Gideon Gerzon

Robert P Knight

Jose Yallouz

Francis McKeen

Regev Shemy

Ilya Albrekht

Scott Dion Rodgers

Shlomo Raikin

Robert Geva

Hisham Shafi

Gur Hildesheim

Meltem Ozsoy

James B Crossland

Michael Mishaeli

Tsvika Kurts

Robert Valentine

Prashant Dewan

Baiju V Patel

Per H Hammarlund

Gautham N Chinya

Asit K Mallick

Moshe Maor

Rinat Rappoport

Oded Lempel

John L Reid

Don Alan Van Dyke

Anton Ivanov

Boris Dolgunov

Sagi Lahav

David M Durham

Efraim Rotem

Eliezer Weissmann

Jason W Brandt

Mohammad A Abdallah

Jesse R Walker

Geoffrey S Strongin

Alon Naveh

Nadav Shulman

Alexander Gendler

John Thomas Shen

Darrell D Boggs

Gila Kamhi

John P Shen

Anil Aggarwal

Doron Orenstein

Zvika Greenfield

Zeev Offen

Ido Ouziel

Roman Surgutchik

Rajesh R Shah

Abraham Mendelson

Oren Lamdan

Dror Caspi

Alberto J Martinez

Ariel Berkovits

Reouven Elbaz

Simcha Gochman

Thierry Pons

Larry O Smith

Guillermo Savransky

Ofir Mulla

Gregory Pribush

Brandon Baker

Oded Oliron Liron

Zelig Wayner

Iris Sorani

Vladimir Beker

Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

Apparatuses, methods, and systems for hashing instructions

A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.

Processors, methods, systems, and instructions to support live migration of protected containers

A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor core coupled to the memory execution unit. The processor core is to receive a request to access a convertible page of the memory. In response to the request, the processor core to determine an intent for the convertible page in view of a page table entry (PTE) corresponding to the convertible page. The intent indicates whether the convertible page is to be accessed as at least one of a secure page or a non-secure page.

Supporting secure memory intent

Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.

Systems and methods for intellectual property-secured, remote debugging

Processors in computerized systems can be targeted by hostile actors seeking to bypass security policies and may employ published or otherwise known vulnerabilities. Embodiments may include security subsystems and methods of operation that identify known vulnerabilities during execution and implement countermeasures or enforce security policies.

Binary translation for hardened software security

A processor or system includes a processor core to execute a set of instructions to determine that a memory encryption mode is enabled. The memory encryption mode is to cause data stored to memory to be encrypted and data retrieved from the memory to be decrypted. The processor core is further to determine that a debug mode has been enabled and, responsive to a determination that the debug mode has been enabled, generate a second encryption key different than a first encryption key employed before reboot of a computing system. The processor core is further to transmit the second encryption key to a cryptographic engine for use in encryption and decryption of the data according to the memory encryption mode.

Preventing unauthorized access to encrypted memory

Secure memory repartitioning technologies are described. Embodiments of the disclosure may include a processing device including a processor core and a memory controller coupled between the processor core and a memory device. The memory device includes a memory range including a section of convertible pages that are convertible to secure pages or non-secure pages. The processor core is to receive a non-secure access request to a page in the memory device, responsive to a determination, based on one or more secure state bits in one or more secure state bit arrays, that the page is a secure page, insert an abort page address into a translation lookaside buffer, and responsive to a determination, based on the one or more secure state bits in the one or more secure state bit arrays, that the page is a non-secure page, insert the page into the translation lookaside buffer.

Secure memory repartitioning technologies

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Haifa, Israel

Ittai Anati