Nec Corporation

Itsurou Taniyoshi

Koichi Kitamura

Syuji Matsuo

Tetsuo Saitoh

The present invention provides a multiplying circuit comprising: an oscillation control circuit for alternately activating first and second oscillation control signals for every clocks of an input clock signal; a first pulse signal generator circuit connected to the oscillation control circuit for receiving the first oscillation control signal so that the first pulse signal generator circuit generates a first multiplied clock signal having a higher frequency than the input clock signal only when the first oscillation control signal is in an activated state; a second pulse signal generator circuit connected to the oscillation control circuit for receiving the second oscillation control signal so that the second pulse signal generator circuit generates a second multiplied clock signal having a higher frequency than the input clock signal only when the second oscillation control signal is in an activated state; and an output circuit connected to the first and second pulse signal generator circuits for receiving the first and second multiplied clock signals and selectively outputting the first and second multiplied clock signals as an multiplied output clock signal.

Clock signal multiplier circuit for a clock signal generator circuit

In a digital phase locked loop, a coarse stepsize variable delay line and a fine stepsize variable delay line are connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits and lower significant bits. The delayed clock pulse is delivered to the input of a clock tree through which the clock pulse propagates and are supplied to various parts of an integrated circuit chip. A phase detector provides a phase comparison between the reference clock pulse and a delayed clock pulse appearing at one of the outputs of the clock tree. A delay controller counts the reference clock pulse to produce a count value, and increments or decrements the count value in accordance with the output of the phase detector. The up-down count value is supplied as the higher and lower significant bits to the coarse and fine stepsize variable delay lines at such longer intervals than the intervals at which the reference clock pulse occurs, so that the delayed clock pulse is allowed a sufficient time to propagate through the clock tree.

Growing community of inventors

Kanagawa, Japan

Itsurou Taniyoshi